LP5569ARTWR datasheet(56/93 Pages) TI2

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LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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Table 46. MISC Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

int_clk_en

R/W

Internal 32-kHz clock-enable select

0 = External 32-kHz clock is used from CLK input pin (default)

1 = Internal 32-kHz oscillator is enabled

Note: This bit is STATIC and should only be changed when

CONFIG.CHIP_EN = 0.

8.6.1.32 ENGINE1_PC Register (Address = 30h) [reset = 0h]

ENGINE1_PC is shown in Figure 58 and described in Table 47.

Return to Summary Table.

Engine1 Program Counter Register

Figure 58. ENGINE1_PC Register

engine1_pc

R/W-0h

Table 47. ENGINE1_PC Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

engine1_pc

R/W

Program counter starting value for program execution engine 1.

8.6.1.33 ENGINE2_PC Register (Address = 31h) [reset = 0h]

ENGINE2_PC is shown in Figure 59 and described in Table 48.

Return to Summary Table.

Engine2 Program Counter Register

Figure 59. ENGINE2_PC Register

engine2_pc

R/W-0h

Table 48. ENGINE2_PC Register Field Descriptions

Bit

Field

Type

Reset

Description

7–0

engine2_pc

R/W

Program counter starting value for program execution engine 2.

8.6.1.34 ENGINE3_PC Register (Address = 32h) [reset = 0h]

ENGINE3_PC is shown in Figure 60 and described in Table 49.

Return to Summary Table.

Engine3 Program Counter Register

Figure 60. ENGINE3_PC Register

engine3_pc

R/W-0h

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