LP5569ARTWR datasheet(20/93 Pages) TI2

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CLK

GPIO/TRIG/INT

VIN

ADDR

CLK

GPIO/TRIG/INT

VIN

ADDR

CLK

GPIO/TRIG/INT

VIN

ADDR

CLK

GPIO/TRIG/INT

VIN

ADDR

VIN

Set up as

Clock master

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

VIN

SDA

SCL

SDA

VIN

SDA

SCL

SDA

SCL

V1P8

1.8V

LP5569

SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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Product Folder Links: LP5569

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3. Set the chip_en bit in the CONFIG register = 1 and the LP5569 device to the NORMAL state.

4. Wait at least 500 µs.

5. Enable all LEDs, and set brightness to 100%.

6. Set the LED_SHORT_TEST bit = 1 in the MISC2 register (address 33h).

7. Wait at least 500 µs.

8. Check the fault status of the LED Fault1 and LED Fault2 registers.

9. Set the LED_SHORT_TEST bit = 0 in in the MISC2 register (address 33h).

10. Set all LEDs to 0% brightness.

8.3.6 Clock Generation and Synchronization

The LP5569 device can generate a 32-kHz clock signal and use it for synchronizing multiple devices. The CLK

pin is configured as an input by default. When the EN_CLK_OUT bit = 1 in the IO_CONTROL register (address

3Dh) the LP5569 device drives the CLK pin using its 32-kHz oscillator.

Figure 19. Synchronizing Multiple Devices Using the Clock Generator

8.3.7 GPIO/TRIG/INT Multifunctional I/O

The GPIO/TRIG/INT pin is configured by the GPIO_CONFIG bits in the IO_CONTROL register (address 3Dh).

The default configuration for this pin is the INT function.

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