LP5569ARTWR datasheet(23/93 Pages) TI2

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LP5569

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SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017

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8.5 Programming

8.5.1 I2C Interface

The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the

device. This protocol uses a two-wire interface for bidirectional communications between the devices connected

to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on

the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates

or receives the serial clock, SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere

on the line and remain HIGH even when the bus is idle. Note: the CLK pin is not used for serial bus data

transfer.

8.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when clock signal is LOW.

Figure 21. Data Validity Diagram

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition

is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is

defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates

START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP

condition. During data transmission, the bus master can generate repeated START conditions. First START and

repeated START conditions are functionally equivalent.

8.5.1.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by

the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP5569 device

pulls down the SDA line during the ninth clock pulse, signifying an acknowledge. The LP5569 device generates

an acknowledge after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

After the START condition, the bus master sends a device address. This address is seven bits long followed by

an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1

indicates a READ. The second byte selects the register to which the data is to be written. The third byte contains

data to write to the selected register.

8.5.1.4 I2C Slave Addressing

The LP5569 slave address is defined by connecting GND, SCL, SDA, or VIN to the ADDR pin. A total of four

slave addresses can be realized by combinations when GND, SCL, SDA, or VIN is connected to the ADDR pin

(see Table 2).

The LP5569 device is available in two versions (LP5569 and LP5569A). Each version has four possible address

settings, which allows up to eight devices sharing the same I2C bus as shown in Table 2. Values are in 7-bit

slave ID format. The LP5569 device responds to slave address 40h regardless of the setting of the ADDR pin

and device version. Global writes to address 40h can be used for configuring all devices simultaneously. The

LP5569 device supports global read using slave address 40h; however, the data read is only valid if all LP5569

devices on the I2C bus contain the same value in the register read.

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