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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP5569ARTWR датащи(PDF) 41 Page - Texas Instruments |
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LP5569ARTWR датащи(HTML) 41 Page - Texas Instruments |
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41 / 93 page  41 LP5569 www.ti.com SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017 Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Figure 28. LED_ENGINE_CONTROL1 Register 7 6 5 4 3 2 1 0 ch1_exec ch2_exec ch3_exec RESERVED R/W-0h R/W-0h R/W-0h R/W-0h Table 17. LED_ENGINE_CONTROL1 Register Field Descriptions Bit Field Type Reset Description 7–6 ch1_exec R/W 0h Engine 1 program execution control 00 = Hold: PC can be read or written only in this mode. (default) 01 = Step. Execute one instruction and return to hold mode. 10 = Free run. Start program from PC. 11 = Execute once. Execute one instruction but don't increment PC. 5–4 ch2_exec R/W 0h Engine 2 program execution control 00 = Hold: PC can be read or written only in this mode. (default) 01 = Step. Execute one instruction and return to hold mode. 10 = Free run. Start program from PC. 11 = Execute once. Execute one instruction but don't increment PC. 3–2 ch3_exec R/W 0h Engine 3 program execution control 00 = Hold: PC can be read or written only in this mode. (default) 01 = Step. Execute one instruction and return to hold mode. 10 = Free run. Start program from PC. 11 = Execute once. Execute one instruction but don't increment PC. 1–0 RESERVED R/W 0h 8.6.1.3 LED_ENGINE_CONTROL2 Register (Address = 2h) [reset = 0h] LED_ENGINE_CONTROL2 is shown in Figure 29 and described in Table 18. Return to Summary Table. LED Engine Control Register 2 Operation modes are defined in this register. DISABLED: Engines each can be configured to be disabled independently. When disabled, the program counter per ENGINEx_PC is set to 0 and the engine does not execute instructions. LOAD PROGRAM: Writing to program memory is allowed only when the engine is in the load-program operation mode and the engine-busy bit (register 3C) is not set. The host should check the engine-busy bit before writing to program memory or allow at a least 1-ms delay after entering the load mode before memory write, to ensure initialization. If any engine is set to the load-program mode, then the other engines should be set either to the disabled or load-program mode, because they are inhibited from executing instructions while loading the SRAM. The load-program mode also resets the program counter of the respective engine. The load-program mode can only be entered from the disabled mode. RUN PROGRAM: The run-program mode executes the instructions stored in the program memory. Execution register (LED_ENGINE_CONTROL1) bits define how the program is executed (hold, step, free-run or execute once). HALT: Instruction execution aborts immediately and engine operation halts. Figure 29. LED_ENGINE_CONTROL2 Register 7 6 5 4 3 2 1 0 ch1_mode ch2_mode ch3_mode RESERVED R/W-0h R/W-0h R/W-0h R/W-0h Table 18. LED_ENGINE_CONTROL2 Register Field Descriptions Bit Field Type Reset Description 7–6 ch1_mode R/W 0h Engine 1 operation mode 00 = Disabled (default) 01 = Load program to SRAM 10 = Run program 11 = Halt |
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