SPC563M60X datasheet(18/128 Pages) STMICROELECTRONICS

18 / 128 page

Overview

SPC563M64x, SPC563M60x

18/128

DocID14642 Rev 12

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Programmable clock source: system clock or oscillator clock

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Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0



Two FlexCAN

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One with 32 message buffers; the second with 64 message buffers

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Full implementation of the CAN protocol specification, Version 2.0B

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Programmable acceptance filters

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Short latency time for high priority transmit messages

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Arbitration scheme according to message ID or message buffer number

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Listen only mode capabilities

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Programmable clock source: system clock or oscillator clock

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Message buffers may be configured as mailboxes or as FIFO



Nexus port controller (NPC)

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Per IEEE-ISTO 5001-2003

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Real time development support for Power Architecture core and eTPU engine

through Nexus class 2/1

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Read and write access (Nexus class 3 feature that is supported on this device)

– Run-time access of entire memory map

– Calibration

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Support for data value breakpoints / watchpoints

– Run-time access of entire memory map

– Calibration

– Table constants calibrated using MMU and internal and external RAM

– Scalar constants calibrated using cache line locking

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Configured via the IEEE 1149.1 (JTAG) port



IEEE 1149.1 JTAG controller (JTAGC)

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IEEE 1149.1-2001 Test Access Port (TAP) interface

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5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

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5-bit instruction register that supports additional public instructions

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Three test data registers: a bypass register, a boundary scan register, and a

device identification register

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Censorship disable register. By writing the 64-bit serial boot password to this

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TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry



On-chip Voltage Regulator for single 5 V supply operation

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On-chip regulator 5 V to 3.3 V for internal supplies

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On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core

logic



Low-power modes

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SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz),

with modules (including the PLL) selectively disabled in software

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STOP Mode. System clock stopped to all modules including the CPU. Wake-up

timer used to restart the system clock after a predetermined time

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