SPC563M60X datasheet(92/128 Pages) STMICROELECTRONICS

92 / 128 page

Electrical characteristics

SPC563M64x, SPC563M60x

92/128

DocID14642 Rev 12

4.11

Temperature sensor electrical characteristics

4.12

eQADC electrical characteristics

Note:

ADC performance is affected by several environmental elements, such as quality of the

input signal source, presence of noise sources and quality of the PCB layout.

The DC or Static parameters (DNL, INL, OFFSET, GAIN, and TUE) are measured using

methods that provide a very accurate evaluation using averaging.

The AC or Dynamic parameters (SNR, THD, SFDR, SINAD) are determined using a full

scale peak-peak sine wave of 1kHz frequency at the input of the ADC.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the fLOR

window.

fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced

mode.

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER

percentage for a given interval.

Proper PC board layout procedures must be followed to achieve specifications.

10. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either

fCS or fDS (depending on whether center spread or down spread modulation is enabled).

11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.

12. Proper PC board layout procedures must be followed to achieve specifications.

13. This parameter is guaranteed by design rather than 100% tested.

14. VIHEXT cannot exceed VRC33 in external reference mode.

15. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

16. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

Table 29. Temperature sensor electrical characteristics

Symbol

Parameter

Conditions

Value

Unit

Min

Typical

Max

—CC

Temperature

monitoring range

–40

—

150

°C

—

C Sensitivity

—

6.3

—

mV/°C

—

Accuracy

TJ = –40 to 150 °C

–20

—

°C

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