SPC563M60X datasheet(8/128 Pages) STMICROELECTRONICS

8 / 128 page

Overview

SPC563M64x, SPC563M60x

8/128

DocID14642 Rev 12

Overview

This document provides electrical specifications, pin assignments, and package diagrams

for the SPC563Mxx series of microcontroller units (MCUs). For functional characteristics,

refer to the SPC563Mxx Microcontroller Reference Manual.

The SPC563Mxx series microcontrollers are system-on-chip devices that are built on Power

Architecture® technology and:



Are 100% user-mode compatible with the Power Architecture instruction set



Contain enhancements that improve the architecture’s fit in embedded applications



Include additional instruction support for digital signal processing (DSP)



Integrate technologies such as an enhanced time processor unit, enhanced queued

analog-to-digital converter, Controller Area Network, and an enhanced modular input-

output system



Operating Parameters

–

Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)

–

–40

C – 150 C junction temperature operating range

–

Low power design

Less than 400 mW power dissipation (nominal)

Designed for dynamic power management of core and peripherals

Software controlled clock gating of peripherals

Low power stop mode, with all clocks stopped

–

Fabricated in 90 nm process

–

1.2 V internal logic



High performance e200z335 core processor



Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)



Enhanced direct memory access (eDMA) controller



Interrupt controller (INTC)

–

191 peripheral interrupt request sources, plus 165 reserved positions

–

Low latency—three clocks from receipt of interrupt request from peripheral to

interrupt request to processor



Frequency Modulating Phase-locked loop (FMPLL)



Calibration bus interface (EBI) (available only in the calibration package)



System integration unit (SIU) centralizes control of pads, GPIO pins and external

interrupts.



Error correction status module (ECSM) provides configurable error-correcting codes

(ECC) reporting



Up to 1.5 MB on-chip flash memory



Up to 94 KB on-chip static RAM



Boot assist module (BAM) enables and manages the transition of MCU from reset to

user code execution from internal flash memory, external memory on the calibration

bus or download and execution of code via FlexCAN or eSCI.

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