SPC563M60X datasheet(9/128 Pages) STMICROELECTRONICS

9 / 128 page

DocID14642 Rev 12

9/128

SPC563M64x, SPC563M60x

Overview

127



Periodic interrupt timer (PIT)

–

32-bit wide down counter with automatic reload

–

4 channels clocked by system clock

–

1 channel clocked by crystal clock



System timer module (STM)

–

32-bit up counter with 8-bit prescaler

–

Clocked from system clock

–

4 channel timer compare hardware



Software watchdog timer (SWT) 32-bit timer



Enhanced modular I/O system (eMIOS)

–

16 standard timer channels (up to 14 channels connected to pins in LQFP144)

–

24-bit timer resolution



Second-generation enhanced time processor unit (eTPU2)

–

High level assembler/compiler

–

Enhancements to make ‘C’ compiler more efficient

–

New ‘engine relative’ addressing mode



Enhanced queued A/D converter (eQADC)

–

2 independent on-chip RSD Cyclic ADCs

–

Up to 34 input channels available to the two on-chip ADCs

–

4 pairs of differential analog input channels



2 deserial serial peripheral interface modules (DSPI)

–

SPI provides full duplex communication ports with interrupt and DMA request

support

–

Deserial serial interface (DSI) achieves pin reduction by hardware serialization

and deserialization of eTPU, eMIOS channels and GPIO



2 enhanced serial communication interface (eSCI) modules



2 FlexCAN modules



Nexus port controller (NPC) per IEEE-ISTO 5001-2003 standard



IEEE 1149.1 JTAG controller (JTAGC)

2.1

Device comparison

Table 2. SPC563Mxx family device summary

Feature

SPC563M64

SPC563M60

Flash memory size (KB)

1536

1024

Total SRAM size (KB)

Standby SRAM size (KB)

Processor core

32-bit e200z335

with SPE and FPU

support

32-bit e200z335

with SPE and FPU

support

Core frequency (MHz)

64/80

40/64/80

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