DAC80504 datasheet(35/50 Pages) TI2

35 / 50 page

DAC80504, DAC70504, DAC60504

www.ti.com

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

Product Folder Links: DAC80504 DAC70504 DAC60504

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8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]

Figure 71. BRDCAST Register

BRDCAST-DATA[15:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. BRDCAST Register Field Descriptions

Bit

Field

Type

Reset

Description

15:0

BRDCAST-DATA[15:0]

R/W

0x0000

Writing to the BRDCAST register forces those DAC channels

that have been set to broadcast in the SYNC register to update

their active data register with the BRDCAST-DATA value.

Data are MSB aligned in straight binary format and follows the

format below:

DAC80504: { DATA[15:0] }

DAC70504: { DATA[13:0], x, x }

DAC60504: { DATA[11:0], x, x, x, x }

x – Don’t care bits

8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]

Figure 72. STATUS Register

Reserved

REF-

ALM

—

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15:1

Reserved

—

Reserved for factory use.

REF-ALM

Reference alarm bit. Reads 1 when the difference between

VREF/DIV and VDD is below the required minimum analog

threshold. Reads 0 otherwise.

8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]

Figure 73. DACx Register

DACx-DATA[15:0]

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. DACx Register Field Descriptions

Bit

Field

Type

Reset

Description

15:0

DACx-DATA[15:0]

R/W

0x0000 or

0x8000

Stores the 16- or 14-bit data to be loaded to DACx in MSB

aligned straight binary format. The default value is determined

by the RSTSEL pin.

Data follows the format below:

DAC80504: { DATA[15:0] }

DAC70504: { DATA[13:0], x, x }

DAC60504: { DATA[11:0], x, x, x, x }

x – Don’t care bits

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