DAC80504 datasheet(27/50 Pages) TI2

27 / 50 page

DAC80504, DAC70504, DAC60504

www.ti.com

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

Product Folder Links: DAC80504 DAC70504 DAC60504

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The DACx0504 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error

exists, the CRC remainder is zero and data are accepted by the device.

A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a

second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as

shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the

SDO/ALARM pin is configured as a CRC alarm pin.

Table 5. Write Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 0).

CRC-ERROR

Returns a 1 when a CRC error is detected, 0 otherwise.

29:28

Reserved

Echo bits 29:28 from previous access cycle (all zeros).

27:24

A[3:0]

Echo address from previous access cycle.

23:8

DO[15:0]

Echo data from previous access cycle.

7:0

CRC

Calculated CRC value of bits 31:8.

A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The

error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As

in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can

be used to indicate a read command CRC failure.

Table 6. Read Operation Error Checking Cycle

BIT

FIELD

DESCRIPTION

Echo RW from previous access cycle (RW = 1).

CRC-ERROR

Returns a 1 when a CRC error is detected, 0 otherwise.

29:28

Reserved

Echo bits 29:28 from previous access cycle (all zeros).

27:24

A[3:0]

Echo address from previous access cycle.

23:8

DO[15:0]

Readback data requested on previous access cycle.

7:0

CRC

Calculated CRC value of bits 31:8.

8.4.4 Power-Down Mode

The DACx0504 DAC output amplifiers and internal reference can be independently powered down through the

CONFIG register. At power-up all output channels and the device internal reference are active by default. A DAC

output channel in power-down mode is connected internally to GND through a 1-kΩ resistor.

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