DAC80504 datasheet(21/50 Pages) TI2

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REF

OUT

CODE

GAIN

DIV

R-2R

DAC Output

DAC

Buffer

LDAC Trigger

(synchronous mode)

DAC

Active

Serial Interface

DAC Data Register

WRITE

READ

(asynchronous mode)

VOUT

Gain

(×1 or ×2)

GND

2.5-V

Reference

REF

REF Divider

(÷1 or ÷2)

DIV

GAIN

DAC80504, DAC70504, DAC60504

www.ti.com

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

Product Folder Links: DAC80504 DAC70504 DAC60504

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8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC)

Each output channel in the DACx0504 consists of an R-2R ladder architecture followed by an output buffer

amplifier. Figure 57 shows a block diagram of the DAC architecture.

Figure 57. DACx0504 DAC Block Diagram

8.3.1.1 DAC Transfer Function

The input data are written to the individual DAC data registers in straight binary format. After a power-on or a

reset event, all DAC registers are set to either zero code or midscale code, as determined by the RSTSEL pin.

The DAC transfer function is given by Equation 1.

where

•

CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to 2

n –

•

VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external

one.

•

n = resolution in bits. Either 16 (DAC80504), 14 (DAC70504), or 12 (DAC60504).

•

DIV = 1 or 2 as set by the REFDIV pin after a reset event or by the REF-DIV bit in the GAIN register.

•

GAIN = 1 or 2 as set by the GAIN pin after a reset event or by the BUFF-GAIN bit for that DAC channel in the

GAIN register.

(1)

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