DAC80504 datasheet(26/50 Pages) TI2

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SDI

SDO

SCLK

DACx0504

SDI

SDO

SCLK

SDI

SDO

SCLK

DAC80504, DAC70504, DAC60504

SBAS871C – AUGUST 2017 – REVISED JANUARY 2019

www.ti.com

Product Folder Links: DAC80504 DAC70504 DAC60504

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8.4.2 Daisy-Chain Operation

For systems that contain more than one DACx0504 devices, the SDO pin can be used to daisy-chain them

together. Daisy-chain operation is useful in reducing the number of serial interface lines.

The first falling edge on the CS pin starts the operation cycle. If more than 24 SCLK pulses are applied while the

CS pin is kept low, the data ripples out of the shift register and is clocked out on the SDO pin either on the falling

edge or rising edge of SCLK according to the FSDO bit. By connecting the SDO output of the first device to the

SDI input of the next device in the chain, a multiple-device interface is constructed. Each device in the system

requires 24 clock pulses. As a result the total number of clock cycles must be equal to 24 × N, where N is the

total number of DACx0504 devices in the daisy chain. When the serial transfer to all devices is complete the CS

signal is taken high. This action transfers the data from the serial peripheral interface (SPI) shift registers to the

internal registers of each device in the daisy chain and prevents any further data from being clocked into the

input shift register.

Figure 61. Daisy-Chain Layout

8.4.3 Frame Error Checking

If the DACx0504 is used in a noisy environment, error checking can be used to check the integrity of SPI data

communication between the device and the host processor. This feature can be enabled by setting the CRC-EN

bit in the CONFIG register.

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111).

When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are

appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in

Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the

32-bit cycle.

Table 4. Error Checking Serial Interface Access Cycle

BIT

FIELD

DESCRIPTION

Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a

write operation. R/W = 1 sets a read operation.

CRC-ERROR

Reserved bit. Set to zero.

29:28

Reserved

Reserved bits. Must be filled with zeros.

27:24

A[3:0]

23:8

DI[15:0]

Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with

address A[3:0]. If a read command, the data cycle bits are don’t care values.

7:0

CRC

8-bit CRC polynomial.

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