LM5064PMHSLASHNOPB datasheet(3/64 Pages) TI2

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LM5064

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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

PIN DESCRIPTIONS (continued)

Pin#

Name

Description

SENSE

Current limit and power limit sense input. SENSE provides a direct connection to the MOSFET source and current

sense resistor voltage to detect current limit and power limit events. This unfiltered signal will allow the LM5064 to

quickly respond during over-current or over-power events.

SENSE_K

Current telemetry Kelvin sense positive input. SENSE_K is the positive input to a precision differential current sense

amplifier. Connecting SENSE_K to the positive terminal of the current sense resistor will provide an accurate

current telemetry signal.

VEE_K

Current telemetry Kelvin sense negative input. The VEE_K pin is the negative input to a precision differential

current sense amplifier. Connecting VEE_K to the negative terminal of the current sense resistor will provide an

accurate current signal.

VEE

Negative supply input. Connect the VEE pin to the negative voltage supply rail. Use a small ceramic bypass

capacitor (0.1 µF) from the VEE pin to the VCC pin to suppress transient current spikes when the load switch is

turned off. The operational voltage range for the VEE pin is -10V to -80V. The VEE pin absolute maximum voltage

is -100V.

SDAI

SMBus data input. The SDAI pin is designed to read PMBus commands using the SMBus communication protocol.

SDAI can be connected to SDAO if desired.

SDAO

SMBus data output. The SDAO pin is designed to transmit PMBus commands using the SMBus communication

protocol. SDAO can be connected to SDAI if desired.

SCL

SMBus clock input.

SMBA

SMBus alert. This pin is connected to an open drain MOSFET which pulls the pin to VEE if a fault is detected.

VREF

Internal ADC reference output. Connect a 1 µF capacitor from the VREF pin to VEE to filter noise imposed on the

internal reference output.

DIODE

Positive diode sense. The DIODE pin should be connected to the anode of a diode whose cathode is connected to

VEE for temperature monitoring.

VAUX

Auxiliary pin allows voltage telemetry from an external source. Full scale input of 2.97V.

ADR2

Address pin 2. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the

LM5064.

ADR1

Address pin 1 The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the

LM5064.

ADR0

Address pin 0. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the

LM5064.

VDD

Internal 4.9V sub-regulator output. VDD must be connected and closely coupled to VEE through a 1 µF ceramic

bypass capacitor.

Current limit threshold input. The LM5064 detects current limit events by sensing the voltage across a series

resistor. The current limit threshold is set to 26 mV by connecting CL to VDD and 50 mV when CL is connected to

VEE.

RETRY

Retry selction pin. Connecting RETRY to VDD sets the LM5064 to lockout after a fault condition is detected.

Connecting RETRY to VEE sets the LM5064 to retry after a fault condition.

TIMER

Timing input. Set the insertion time delay and the fault timeout period by connecting a capacitor from the TIMER pin

to VEE. The restart time is also set through the TIMER pin when in restart mode.

PWR

Power limit input. Connecting a resistor from PWR to VEE sets the maximum power dissipation allowed in the

external MOSFET switch. Power is calculated using the current information through the current sense resistor and

voltage sensed across the MOSFET.

OUT

Output voltage sense input. The OUT pin is used to sense the output voltage and calculate the power across the

MOSFET switch.

No connect. This pin is not internally connected and should not be connected to any signal or power rail.

PGD

Power good monitor output. Open-drain output pulls low during over-current, UVLO, and OVLO. An external pull-up

resistor to VDD or external rail is required.

Exposed pad. Connect to PCB VEE plane using multiple thermal vias.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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