LM5064PMHSLASHNOPB datasheet(13/64 Pages) TI2

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LM5064

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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

FUNCTIONAL DESCRIPTION

The LM5064 is designed to control the in-rush current to the load upon insertion of a circuit card into a live

backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply and the dv/dt

of the voltage applied to the load. The effect from the insertion event on other circuits in the system is minimized,

preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be

implemented using the LM5064.

In addition to a programmable current limit, the LM5064 monitors and limits the maximum power dissipation in

the series pass device (Q1) to maintain operation within the device’s Safe Operating Area (SOA). Either current

limiting or power limiting for an extended period of time (user defined) results in the shutdown of the series pass

device. In this event, the LM5064 can latch off or repetitively retry based on the hardware setting of the RETRY

pin. Once started, the number of retries can be set to 0, 1, 2, 4, 8, 16, or infinite. The circuit breaker function

quickly switches off the series pass device upon detection of a severe over-current condition. Programmable

under-voltage lockout (UVLO) and over-voltage lockout (OVLO) circuits shut down the LM5064 when the system

input voltage (VSYS) is outside the desired operating range.

The telemetry capability of the LM5064 provides intelligent monitoring of the input voltage, output voltage, input

current, input power, temperature, and an auxiliary input. The LM5064 also provides a peak capture of the input

power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning

thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power and

temperature via the PMBus interface. Additionally, the LM5064 is capable of detecting damage to the external

MOSFET, Q1.

Operating Voltage

The LM5064 operating voltage is the voltage supplied between VCC and VEE (VCC-VEE) which has an

operating range of 10V to 80V with a 100V transient capability. All signals to the IC are referenced to the VEE

voltage which acts as the effective return path for the IC.

Power Up Sequence

Referring to Figure 2, as the system voltage (VSYS) initially increases, the external N-channel MOSFET (Q1) is

held off by an internal 111 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin

prevents an inadvertent turn on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the

TIMER pin is initially held at VEE. When the operating voltage of the LM5064 (VCC - VEE) reaches the PORIT

threshold, the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by

a 4.8 µA current source, and Q1 is held off by a 4.1 mA pull-down current at the GATE pin regardless of the input

voltage. The insertion time delay allows ringing and transients on VSYS to settle before Q1 is enabled. The

insertion time ends when the TIMER pin voltage reaches 3.9V. CT is then quickly discharged by an internal 1.5

mA pull-down current. The GATE pin then switches on Q1 when the operating voltage exceeds the UVLO

threshold. If the operating voltage is above the UVLO threshold at the end of the insertion time,(t1 in Figure 2) the

GATE pin sources 52 µA to charge the gate capacitance of Q1. The maximum voltage on GATE is limited by an

internal 12.6V zener diode to VEE.

As the voltage at the OUT pin transitions to VSYS, the LM5064 monitors the drain current and power dissipation of

MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the

load. During the in-rush limiting interval (t2 in Figure 2), an internal 74 µA fault timer current source charges CT. If

Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER

pin reaches 3.9V, the 74 µA current source is switched off, and CT is discharged by the internal 2.4 µA current

sink (t3 in Figure 2). The in-rush limiting will no longer engage unless a current-limit condition occurs.

If the TIMER pin voltage reaches 3.9V before in-rush current limiting or power limiting ceases during t2, a fault is

declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode.

The LM5064 will assert the SMBA pin after the operating voltage has exceeded the POR threshold to indicate

that the volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the

MFR_SPECIFIC_17 register (E1h) indicates default configuration of warning thresholds and device operation and

will remain high until a CLEAR_FAULTS command is received.

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