LM5064PMHSLASHNOPB datasheet(29/64 Pages) TI2

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LM5064

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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

A typical value of Rpin can be 22Ω to effectively limit the pin current during extreme negative voltage spikes. If

schottky diodes are used, they only need to be applied to SENSE_K, SENSE, and OUT. Each schottky diode

return pin should be coupled closely with the VEE plane to provide the most effective clamping. The schottky

diode at OUT should be able to withstand at least 100V. VEE_K needs a series resistor even though it’s not

subjected to negative voltage spikes in order to balance the differential current sense voltage signal. Protecting

the SENSE_K, SENSE, and OUT pins from negative voltage spikes will facilitate a robust hot-swap circuit and

smooth operation during extreme reverse current surge events.

PC BOARD GUIDELINES

The following guidelines should be followed when designing the PC board for the LM5064:

- Place the LM5064 close to the board’s input connector to minimize trace inductance from the connector to the

MOSFET (Q1).

- Place a TVS (Z1), directly adjacent to the VCC and VEE pins of the LM5064 to help minimize voltage transients

which may occur on the input supply line. The TVS should be chosen such that the peak VSYS is just lower the

TVS reverse-bias voltage. Transients of 20 volts or greater over the nominal input voltage can easily occur when

the load current is shut off. A small capacitor may be sufficient for low current sense applications (I < 2A). It is

recommended to test the VSYS input voltage transient performance of the circuit by current limiting or shorting the

load and measuring the peak input voltage transient.

- Place a 1 µF ceramic capacitor as close as possible to VREF pin.

- Place a 1 µF ceramic capacitor as close as possible to VDD pin.

- Minimize the inductance between the SENSE, SENSE_K, VEE_K, and VEE pins. There are anti-parallel diodes

between these pins so any voltage greater than 0.3V in either polarity will cause significant current flow through

the diodes, which can result in device failure. Do not place any resistors between these nodes.

- Minimize the impedance between the VEE_K and SENSE_K pins. There are anti-parallel diodes between these

pins so any voltage greater than 0.3V in either polarity will cause significant current flow through the diodes,

which can result in device failure.

- The sense resistor (RS) should be placed close to the LM5064. A trace should connect the VEE source pin and

OUT drain pad of Q1 to the sense resistor to VEE_K and SENSE_K pins, respectively. Connect RS using the

Kelvin techniques shown in Figure 7.

- The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and

close to each other to minimize loop inductance.

- The termination connections for the various components around the LM5064 should be connected directly to

each other, and to the LM5064’s VEE pin connection, and then connected to VSYS at one point. Do not connect

the various component terminations to each other through the high current VSYS line.

- Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and

turn-off.

- The board’s edge connector can be designed such that the LM5064 detects via the UVLO/EN pin that the

board is being removed, and responds by turning off the load before the supply voltage is disconnected. For

example, in Figure 18, the voltage at the UVLO/EN pin goes to VEE before VSYS is removed from the LM5064 as

a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system

voltage is applied to the LM5064’s VSYS pin before the UVLO voltage is taken high, thereby allowing the LM5064

to turn on the output in a controlled fashion.

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