LM5064PMHSLASHNOPB datasheet(21/64 Pages) TI2

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LM5064

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SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

POWER LIMIT THRESHOLD

The LM5064 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the

current in RS) and the VDS of Q1 (OUT to SENSE pins). The resistor at the PWR pin (RPWR) sets the maximum

power dissipation for Q1, and is calculated from the following equation:

(2)

where PMOSFET(LIM) is the desired power limit threshold for Q1, and RS is the current sense resistor described in

the CURRENT LIMIT (RS) section. For example, if RS is 3 mΩ, VIN = 48V, and the desired power limit threshold

is 80W, RPWR calculates to 30.1 kΩ (standard 1% value). If Q1’s power dissipation reaches the threshold Q1’s

gate is modulated to regulate the load current, keeping Q1’s power from exceeding the threshold. For proper

operation of the power limiting feature, RPWR must be ≤150 kΩ. While the power limiting circuit is active, the fault

timer is active as described in the Fault Timer & Restart section. Typically, power limit is reached during startup,

or if the output voltage falls due to a severe over-load or short circuit. The programmed maximum power

dissipation should have a reasonable margin from the maximum power defined by the SOA chart, especially if

retry is enabled, because the MOSFET will be repeatedly stressed during fault restart cycles. The MOSFET

manufacturer should be consulted for guidelines. If the application does not require use of the power limit

function the PWR pin can be left open. The accuracy of the power limit function at turn-on may degrade if a very

low power dissipation limit is set. The reason for this caution is that the voltage across the sense resistor, which

is monitored and regulated by the power limit circuit, is lowest at turn-on when the regulated current is at a

minimum. The voltage across the sense resistor during power limit can be expressed as follows:

(3)

where ILIM is the current in RS, and VDS is the voltage across Q1. For example, if the power limit is set at 80W

with RS = 3 mΩ, and VDS = 48V the sense resistor voltage calculates to 5.0 mV, which is comfortably regulated

by the LM5064. However, if the power limit is set lower (e.g., 25W), the sense resistor voltage calculates to 1.6

mV. At this low level noise and offsets within the LM5064 may degrade the power limit accuracy. To maintain

accuracy, the sense resistor voltage should not be less than 3 mV.

TURN-ON TIME

The output turn-on time depends on whether the LM5064 operates in current limit, or in both power limit and

current limit, during turn-on.

A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor

(RS). If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS

the circuit operates only at the current limit threshold during turn-on. Referring to Figure 8(A), as the load current

reaches ILIM, the gate-to-source voltage is controlled at GATE to maintain the current at ILIM. As the output

voltage reaches its final value (VDS ≊ 0V) the drain current reduces to its normal operating value. The time for the

OUT pin voltage to transition from zero volts to VSYS is equal to:

(4)

where CL is the load capacitance. For example, if VSYS = -48V, CL = 200 µF, and ILIM = 8.7A, tON calculates to 1.1

ms. The maximum instantaneous power dissipated in the MOSFET is 418W. This calculation assumes the time

from t1 to t2 in Figure 9 (A) is small compared to tON, the load does not draw any current until after the output

voltage has reached its final value, and PGD switches high (Figure 8 (A)). The Fault Timeout Period must be set

longer than tON to prevent a fault shut-down before the turn-on sequence is complete.

If the load draws current during the turn-on sequence (Figure 8 (B)), the turn-on time is longer than the above

calculation, and is approximately equal to:

(5)

where RL is the load resistance. The Fault Timeout Period must be set longer than tON to prevent a fault

shutdown before the turn-on sequence is complete.

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