LM5064PMHSLASHNOPB datasheet(14/64 Pages) TI2

14 / 64 page

TIMER Pin

Load

Current

PGD

UVLO

Limiting

Normal Operation

GATE Pin

Insertion Time

Operating

Voltage

Output

Voltage

VEE

2.4 PA

74 PA

52 PA source

3.9 V

4.1 mA pull- down

4.8PA

1.24V

I LIMIT

VSYS

pull-down

111 mA

VSYS

PORIT

System

Input

Voltage

(VCC± VEE)

LM5064

(OUT Pin)

t 3

t 2

In-rush

t 1

|VSYS|

LM5064

SNVS718E – JUNE 2011 – REVISED FEBRUARY 2013

www.ti.com

Figure 2. Power Up Sequence

Gate Control

A current source provides the charge at the GATE pin to enhance the N-Channel MOSFET’s gate (Q1). During

normal operating conditions (t3 in Figure 2) the gate of Q1 is held charged by an internal 52 µA current source.

The GATE pin peak voltage is roughly 12.6V, which will force a VGS across Q1 of 12.6V under normal operation.

When the system voltage is initially applied, the GATE pin is held low by a 111 mA pull-down current. This helps

prevent an inadvertent turn on of Q1 through its drain-gate capacitance as the applied system voltage increases.

During the insertion time (t1 in Figure 2), the GATE pin is held low by a 4.1 mA pull-down current. This maintains

Q1 in the off-state until the end of t1, regardless of the voltage on VSYS or UVLO/EN. Following the insertion time,

during t2 in Figure 2, the gate voltage of Q1 is modulated to keep the current or power dissipation level from

exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is

charging. If the current and power limiting cease before the TIMER pin reaches 3.9V, the TIMER pin capacitor

then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the

TIMER pin reached 3.9V during t2, the GATE pin is then pulled low by the 4.1 mA pull-down current. The GATE

pin is then held low until either a power up sequence is initiated (RETRY pin to VDD), an automatic retry is

attempted (RETRY pin to VEE or floating), or a PMBus ON/OFF command is initiated. See the Fault Timer &

Restart section. If the operating voltage falls below the UVLO threshold, or rises above the OVLO threshold, the

GATE pin is pulled low by the 4.1 mA pull-down current to switch off Q1.

Submit Documentation Feedback

Product Folder Links: LM5064

LM5064PMH/NOPB датащи(PDF) 14 Page - Texas Instruments

LM5064PMH/NOPB датащи(HTML) 14 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

датащи скачать

ссылки URL