PCF8545ATTSLASHA datasheet(42/72 Pages) NXP

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PCF8545

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Product data sheet

Rev. 1 — 13 November 2013

42 of 72

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

9.3 SPI-bus interface

Data transfer to the device is made via a 3 line SPI-bus (see Table 30). There is no output

data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive.

[1]

The chip enable must not be wired permanently LOW.

9.3.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a byte

with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the subaddress byte.

The subaddress byte opens the communication with a read/write bit and a subaddress.

The subaddress is used to identify multiple devices on one SPI-bus.

After the subaddress byte, a control byte follows (see Section 9.1 on page 36).

Table 30.

Serial interface

Symbol

Function

Description

chip enable input[1]; active LOW

when HIGH, the interface is reset

SCL

serial clock input

input may be higher than VDD

SDI

serial data input

input may be higher than VDD; input data is

sampled on the rising edge of SCL

Fig 32. Data transfer overview

Table 31.

Subaddress byte definition

Bit

Symbol

Value

Description

7R/W

data read or write selection

write data

read data

6 to 5

SA[1:0]

subaddress; other codes cause the device to

ignore data transfer

4 to 0

unused

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