PCF8545ATTSLASHA datasheet(14/72 Pages) NXP

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PCF8545

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Product data sheet

Rev. 1 — 13 November 2013

14 of 72

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

8.1.5 Command: set-MUX-mode

The multiplex drive mode is configured with the bits described in Table 15.

[1]

Default value.

8.1.6 Command: set-bias-mode

The set-bias-mode command allows setting the bias level.

[1]

Default value.

8.1.7 Command: frame-frequency

With the frame-frequency command, the frame frequency for the display can be

configured. The clock frequency determines the frame frequency.

When using an external clock it can be either a 230 kHz or a 9.6 kHz clock signal. The

EFR bit (see Table 10) has to be set according to the external clock frequency.

When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1:

(1)

When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation 2:

(2)

where q is the frequency divide factor (see Table 18).

Remark: fclk(ext) is the external input clock frequency to pin OSCCLK.

Table 15.

Set-MUX-mode - set multiplex drive mode command bit description

Bit

Symbol

Value

Description

7 to 2

000000

fixed value

1 to 0

M[1:0]

00[1], 01

1:8 multiplex drive mode; eight backplanes

1:6 multiplex drive mode; 6 backplanes

1:4 multiplex drive mode; 4 backplanes

Table 16.

Set-bias-mode - set bias mode command bit description

Bit

Symbol

Value

Description

7 to 2

000001

fixed value

1 to 0

B[1:0]

00[1]. 01

1⁄4 bias

1⁄3 bias

1⁄2 bias

Table 17.

Frame-frequency - frame frequency and output clock frequency command bit

description

Bit

Symbol

Value

Description

7 to 5

001

fixed value

4 to 0

FD[4:0]

see Table 18

frequency prescaler

fr LCD



clk ext



-----------------

fr LCD



clk ext



48 q



-----------------

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