PCF8545ATTSLASHA datasheet(38/72 Pages) NXP

38 / 72 page

PCF8545

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Product data sheet

Rev. 1 — 13 November 2013

38 of 72

NXP Semiconductors

PCF8545

Universal LCD driver for multiplex rates up to 1:8

9.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 29.

9.2.5 I2C-bus controller

The PCF8545 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. Device selection depends on the I2C-bus

slave address.

Fig 28. System configuration

Fig 29. Acknowledgement on the I2C-bus

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