MP44019

– CRM/DCM MULTI-MODE PFC CONTROLLER WITH SECOND OVP

MP44019 Rev. 1.0

MonolithicPower.com

24

4/30/2021

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CZ =

1

2πx5xRZ

= 1.1μF

(48)

And CP can be estimated with Equation (49):

CP =

1

2πx50xRZ

= 0.1μF

(49)

For

this

compensation

network,

it

is

recommended for RZ = 30kΩ, CZ = 1µF, and

CP = 220pF

PCB Layout Guidelines

PCB layout is critical for stable operation and

EMI performance, as the device can malfunction

due to noise coupling. For the best results, refer

to Figure 15 and follow the guidelines below:

1. Make power loop 1 and power loop 2 as

small as possible.

2. Do not place the IC in power loop 1 or power

loop 2.

3. Make the areas of high dV/dt junctions (e.g.

the drain of the external primary MOSFET)

as small as possible. Place the IC and control

circuits far away from these areas.

4. Separate the reference ground of the IC and

control signals circuit from the ground of the

power loop. Then connect this signal ground

to the ground of the output capacitor with a

single-point junction.

5. Connect the VCC-to-GND capacitor close to

IC.

6. Connect the FB-to-GND and OVP2-to-GND

capacitors close to the IC.

7. Connect the MAINS-to-GND capacitor close

to the IC. Ensure that the CS wiring does not

cross MAINSIN. Otherwise, the CS noise

may couple to MAINSIN and impact peak

voltage sensing.

8. If the PFC stage is connected to a cascade

DC/DC stage, separate both GNDs with an

output capacitor, so that GND noises do not

interfere with one another.

VOUT

BD1

C1

RIN1

C5

COUT

RZCD

RG

RCS

RO1

Q1

L1

D1

VAC

Cx1

F1

VCC

MP44019

R4

C3

D2

D3

Loop 1

Loop 2

ROV1

ROV2

Figure 15: Recommended PCB Layout