MP44019

– CRM/DCM MULTI-MODE PFC CONTROLLER WITH SECOND OVP

MP44019 Rev. 1.0

MonolithicPower.com

23

4/30/2021

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In this case, it is recommended to place two

100m

Ω 2512 SMT resistors in parallel.

To enhance the anti-interference ability, a 1k

Ω

resistor is connected in series to CS. In addition,

to pass the surge test, ZCD winding is connected

to the ZCD/CS pin through a diode, and RZCD can

be used to obtain the valley signal of the drain

voltage. Generally, RZCD is designed to be equal

to R4 (for example, RZCD = R4 = 4.7kΩ).

A leading edge blanking time of tZCD_LEB (typically

0.3µs) is inserted to filter out the noise ringing on

ZCD winding just after gate turns off.

The auxiliary winding turn ratio can be calculated

with Equation (40):

N≤

VOUT-√2×VAC

MAX

2������������������������_������+VF

=9.6

(40)

Where VAC_MAX is 265VAC.

In this scenario, 26:3 is selected as the winding

ratio.

If the reflected voltage on ZCD winding is below

VZCD_L (typically 0.25V) after the gate turns off,

the AC input voltage can be estimated with

Equation (41):

VAC_LIMIT≥

VOUT−N×(2×VZCD_L+VF)

√2

=273

(41)

Erratic switching may occur if the AC source is

tuned above VAC_LIMIT. In this scenario, a voltage

spike exceeding 0.75V may be generated when

the gate turns off. If this spike lasts for longer

than tZCD_LEB (typically 0.3µs), this means that the

turn-on condition is a result of this spike. The

device immediately starts to counter the timer for

a dead time extension while ignoring the turn-off

time. Finally, this switching cycle becomes

shorter than a normal cycle.

There are three recommendations to attenuate

the spike. This first recommendation is to use a

lower resistance for RZCD and R4 (e.g. a 3kΩ

resistor with a 1206 package).

A second solution is to choose a FET with a

shorter turn-off delay time and turn-off time. The

final recommendation is to increase the BUS

voltage.

The OVP2 Pin

The second OVP voltage (VOVP2 = VOUT + ΔOVP)

can be set by the OVP2 resistors.

Normally, it is recommended to use three 3.3M

Ω

resistors in series for the upper voltage resistor

dividers of OVP2.

The lower voltage resistor divider can be

estimated with Equation (42):

ROV2=

VOVP2×VFB_OVP2

VOVP2-VFB_OVP2

×ROV1=61kΩ (42)

The COMP Pin

Based on the small signal model, the control to

output voltage transfer function (resistive load)

can be estimated with Equation (43):

GVC(s) =

KRAMP

3×KMAIN

2

x

1

2×VOUT×COUT×L

x

1

2

RO×COUT

+s

(43)

Where KMAIN is the MAINSIN voltage divider ratio,

and KRAMP is equal to tON_LL.

In this scenario, GVC can be calculated with

Equation (44):

GVC(s) =

4706.67

s+16.67

(44)

In addition, the voltage error amplifier is a

transconductance

amplifier.

The

voltage

compensation tank is connected from COMP to

GND. A Type-II compensation network is

recommended. The transfer function of the

transconductance amplifier can be calculated

with Equation (45):

GEA(s) = KFBxGM1x

1

CPxs

x

1

CZ×RZ

+s

CZ+CP

CZ×CP×RZ

+s

(45)

Where KFB is the FB voltage divider ratio, and

GM1 is the transconductance value (typically

105µs).

The open voltage loop transfer function can be

calculated with Equation (46):

G(s) = GVC(s)xGEA(s)

(46)

In this scenario, to design a high-stability voltage

loop, it is recommended to make the crossover

frequency 12Hz, as the phase margin must

exceed 45°. 5Hz is the recommended zero value,

and 50Hz should be selected as the pole with

high frequency.

The value of the compensation network can be

calculated with Equation (47):

RZ =

1

KFBxGM1

x10

-ΦVC(12)

20

= 28.5kΩ

(47)

Where CZ can be estimated with Equation (48):