MP44019

– CRM/DCM MULTI-MODE PFC CONTROLLER WITH SECOND OVP

MP44019 Rev. 1.0

MonolithicPower.com

18

4/30/2021

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© 2021 MPS. All Rights Reserved.

Since tON (θ) is generated by an internal ramp

current that is compared to the COMP voltage,

tON (θ) stays constant throughout one AC line

cycle. Meanwhile, REQ behaves like a resistor

load. This means the average input current is

proportional to VAC (θ).

Along with reducing the load, the MP44019

gradually works from CrM to DCM to reduce the

switching loss under light loads.

IL

tON

t

Figure 10: DCM

The average input current in one cycle can be

estimated with Equation (7):



















AC

AC

IN

ON

C

EQ2

v

( )

v

( )

I ( )

t

( ) D ( )

2 L

R

(7)

Where REQ2 can be estimated with Equation (8):









EQ2

ON

C

2L

R

t ( ) D ( )

(8)

And DC can be estimated with Equation (9):









ON

OND

C

ON

OND

D

tt

D ( )

t

t

t

(9)

A dedicated, variable on time control circuit is

integrated into the device. tON can be calculated

with Equation (10):









ON

C

t ( )

D ( )

(10)

Where

ε is a constant defined by the internal

parameters.

REQ2

can

be

estimated

with

Equation (11):







EQ2

2L

R

(11)

REQ2 also behaves like a resistor load, and the

input average current is proportional to VAC (θ).

Mains Compensation

The input power for the boost PFC converter can

be calculated with Equation (12):





2

AC

IN

ON

V

Pt

2L

(12)

This means that the AC transient response is

suboptimal due to the square of the mains input

voltage.

The COMP voltage (VCOMP) can be estimated

with Equation (13):



COMP

2

AC

1

V

V

(13)

VCOMP varies between low-line and high-line. For

general designs, the burst mode load is

determined by VCOMP. In high-line, the converter

enters burst mode even under heavy loads. The

audible noise is created accordingly.

To compensate for the mains input voltage

influence, the MP44019 contains a square of VAC

compensation circuits. The AC peak voltage is

sensed at MAINSIN, and is fed to the generation

of the internal ramp current.

The internal COMP voltage can be estimated

with Equation (14):

  



2

MAIN

COMPI

IN

RAMP

K

V

4 L P

K

(14)

Where KMAIN is the voltage divider ratio of

MAINSIN, and KRAMP is equal to tON_LL (typically

24µs/V).

Figure 11 shows the relationship between tON

and COMP.

24µs

2.1µs

tON

MAINSIN =

1V

MAINSIN =

3.38V

VCOMP_L

VCOMP_H

VCOMP

Figure 11: tON vs. COMP

Over-Current Limit (OCL)

Figure 12 shows the block diagram for over-

current limit (OCL) and over-current protection

(OCP). The current is sensed by the CS pin. The

device can limit the current cycle by cycle when

CS exceeds VOCL (0.5V).