ACT88430 datasheet(33/74 Pages) QORVO

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Data Sheet Rev. G, August 2021 | Subject to change without notice

33 of 74

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ACT88430

Advanced PMU for Microcontrollers and Solid State Drive Applications

also be used as inputs to control different power rail

enable signals. They are configurable, so refer to the

back of the datasheet for their specific functionality for

each CMI. Contact the factory for available options.

They are open drain outputs and are 5.5V tolerant

meaning that they can be pulled up to 5.5V even if

VIO_IN is less than 5.5V.

nRESET

nRESET issues the main reset to the CPU/controller.

nRESET is immediately asserted low when either the

VIN voltage is above or below the UV or OV thresholds

or any valid output supply voltage is below its Power

Good

(POK)

threshold.

After

startup,

nRESET

de-asserts after a programmable delay time after

all outputs are above their respective UVLO thresholds.

The nRESET delay time is controlled by the I2C

bits

nRST_DLY[2:0],

which

programs

the

delay

between 200us and 1ms in 114us steps. nRESET is

configurable, so refer to the CMI Options section in the

back of the datasheet for its specific functionality for

each CMI. nRESET is an open drain output and is 5.5V

tolerant meaning that nRESET can be pulled up to 5.5V

even if VIO_IN is less than 5.5V.

EXT_EN

EXT_EN is used to control an external regulator or to

provide a control signal to other system components.

When the MODE pin = 0 to configure Buck1 as a

standard power supply, EXT_EN is the output of the

ACT88430’s internal BUCK1 enable signal. When the

MODE pin = 1 to configure Buck1 as a bypass switch,

EXT_EN is the output of the bypass switch enable

signal.

The I2C bit EXT_EN_POL controls the EXT_EN polarity.

EXT_EN is active high when EXT_EN_POL is low and

EXT_EN is active low when EXT_EN_POL is high.

EXT_EN is a push-pull CMOS output using VIO_IN

supply. Note that the EXT_EN output is enabled and

valid in all modes of operation. EXT_EN is configurable,

so refer to the CMI Options section in the back of the

datasheet for its specific functionality for each CMI.

EXT_EN is referenced to the VIO_IN pin. It should not

be pulled higher than VIO_IN.

The PG pin shows the status of a regulator’s Power

Good / UV comparator. When the regulator is below the

Power Good threshold, the PG pin is pulled low. When

above the threshold, the PG pin is open drain. The PG

functionality is enabled by default, but can be disabled

by I2C. PG can be disabled by using the appropriate reg-

ulator’s UV_FLTMSK bit. Table 3 shows the possible

regulators that can drive the PG pin.

Table 3: ACT88430 PG Input Choices

Allowable PG Inputs

Buck1

Buck2

Buck3

Buck4

LDO1

LDO2 AND Buck4

LDO3

LDO3 AND Buck4

PG is configurable, so refer to the back of the datasheet

for its specific functionality for each CMI. PG is an open

drain output and is 5V tolerant meaning that PG can be

pulled up to 5.5V even if VIO_IN is less than 5.5V.

STEP-DOWN DC/DC CONVERTERS

General Description

The ACT88430 contains four fully integrated step-down

converters. Buck1 is a 4A output, while Buck2, Buck3,

and Buck4 are 2.5A outputs. All buck converters are

fixed frequency, current-mode controlled, synchronous

PWM converters that achieve peak efficiencies of up to

96.5%. The buck converters switch at 2.25MHz and are

internally compensated, requiring only three small

external components (Cin, Cout, and L) for operation.

They ship with default output voltages that can be

modified via the I2C interface for systems that require

advanced power management functions.

Each buck converter has a dedicated input pin and

power ground pin. Each buck converter should have a

dedicated input capacitor that is optimally placed to

minimize the power routing loops for each buck

converter. Note that even though each buck converter

has separate inputs, all buck converter inputs must be

connected to the same voltage potential.

Buck1 is configurable as a bypass switch for systems

with a 3.3V bus voltage. The bypass switch provides full

sequencing capability by allowing the 3.3V bus to be

used as the input to the other supplies and still be

properly sequenced to the downstream load.

Tie MODE to AGND to configure Buck1 for a switching

power supply. Tie MODE to VIN to configure Buck1 as

a bypass switch. MODE is only sampled when VIN

reaches its UVLO threshold. Changing the MODE pin

after startup has no effect. When Buck1 is configured as

a power supply, EXT_EN is a direct output of the

ACT88430 Buck1 enable signal. When Buck1 is config-

ured as a bypass switch, EXT_EN is a direct output of

the bypass switch enable signal.

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