ACT88430 datasheet(32/74 Pages) QORVO

32 / 74 page

Data Sheet Rev. G, August 2021 | Subject to change without notice

32 of 74

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ACT88430

Advanced PMU for Microcontrollers and Solid State Drive Applications

as either a power good input from an external supply or

a dynamic voltage scaling control input. Configure

EXT_PG as a power good input by setting I2C bit

DVS_EN = 0. When configured as a power good input,

EXT_PG can be used as an input to the nRESETx pins.

EXT_PG polarity is controlled by the EXT_PG_POL bit.

EXT_PG is active high when EXT_PG_POL = 0 and

active low when EXT_PG_POL = 1.

Configure EXT_PG as a dynamic voltage scaling (DVS)

control input by setting I2C bit DVS_EN = 1. When

EXT_PG is de-asserted, all buck regulators regulate to

their VSET0 voltage. When EXT_PG is asserted, the

buck regulators regulate to their VSET1 voltage. Note

that EXT_PG input is only valid for DVS toggling when

the IC is in the ACTIVE state of operation. I2C bit

EXT_PG_POL has no effect in DVS Mode.

EXT_PG is referenced to the VIN pin, and should not

be pulled above VIN. The EXT_PG input has a 10us

bidirectional filter to prevent noise from triggering

unwanted operation.

VIO_IN

VIO_IN is the input bias supply for the IC. Apply an input

voltage between 1.62V and 5.5V. Bypass to AGND with

a high quality, 1uF ceramic capacitor.

MODE

Setting MODE = 0 configures Buck1 as a standard

integrated buck regulator. Setting MODE = 1 configures

Buck1 as an integrated bypass switch. Buck1 can only

operate as a bypass switch when VIN=3.3V. In bypass

mode, the Buck1 P-ch power FET is used to sequence

the 3.3V supply to the downstream load. This provides

full sequencing flexibility for 3.3V systems by allowing

the 3.3V input to be used as the input supply for the

other regulators but still be sequenced in any order for

the downstream loads. Bypass mode is only valid for a

3.3V input voltage. The MODE pin must be tied directly

to VIN or AGND. I2C bit MODE_STAT shows the status

of the MODE pin when it was read at startup.

GPIO

The GPIO pin can be configured as a digital input or an

open drain output. It has multiple uses, including a

sequencing input, sequencing output, status output, or

control input to toggle a supply’s output voltage. Set I2C

bit GPIO_OUT = 0 to configure GPIO as an input. When

using GPIO as an output, GPIO_OUT = 0 configures it

as an open drain output, and GPIO_OUT = 1 configures

it as a logic low output. When used as either an input or

an output, I2C bit GPIO_STAT always provides the real-

time status of the GPIO pin. GPIO_STAT = 0 when

GPIO pin is a logic 0. GPIO_STAT = 1 when GPIO pin

is a logic 1.

GPIO pin is referenced to the VIN pin, and is 5.5V

tolerant meaning that GPIO can go to 5.5V even if VIN

is less than 5.5V.

IRQ

The IRQ pin is an output that issues an interrupt to

the host CPU/Controller when an ACT88430 fault or

warning condition occurs.

IRQ is triggered by:

Die temperature exceeding Thermal Interrupt Threshold

of 135C.

Any buck regulator reaching peak current limit, ILIMSET,

for 16 cycles after softstart.

Any LDO regulator reaching current limit, LDOx_ILIM,

for more than 16us after softstart.

BUCK1 PMOS switch exceeding Current Detection

threshold 75% of ILIMSET when system is configured

in bypass mode.

IRQ is masked by the I2C register 0x00h bit2

(IRQ_nMASK) by default to mask all IRQ conditions. To

enable IRQ functionality, set IRQ_nMASK = 1. IRQ is

an active-low open drain 5.5V compatible output.

POK

POK indicates that the voltage on the VIN pin is inside

the POK UV and OV Interrupt Thresholds. If the VIN

voltage is above or below these values, POK pulls low

to interrupt the host CPU/Controller. POK is masked by

the I2C bit POK_nMASK by default. To enable POK

functionality, set I2C bit POK_nMASK = 1. I2C bits

POK_OV and POK_UV provide real-time UV and OV

status, even when POK is masked. The POK UV and

OV threshold are configurable via the I2C bits

POK_UV_SET and POK_OV_SET.

POK is an open drain output and is 5.5V tolerant

meaning that POK can be pulled up to 5.5V even if

VIO_IN is less than 5.5V.

nRESET_AUX1 and nRESET_AUX2

nRESET_AUX1 and nRESET_AUX2 pins can be used

to signal that the IC is in the SLEEP state or that the

input voltage is above or below the UV or OV threshold.

They can also be tied to one or a combination of the

power supply’s internal POK signals. When asserted by

the internal POK signals they immediately assert. They

follow a programmed delay when de-asserted. The

nRESET_AUX1 delay time is controlled by the I2C bits

RST_AUX1_DLY[2:0],

which

programs

the

delay

between 400us and 2mS in 227us steps. The

nRESET_AUX2 delay time is controlled by the I2C bits

RST_AUX2_DLY[2:0],

which

programs

the

delay

between 200us and 1ms in 114us steps. These pins can

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