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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB1044AI датащи(PDF) 10 Page - Texas Instruments |
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TUSB1044AI датащи(HTML) 10 Page - Texas Instruments |
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10 / 66 page  over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RON_FLAT ON resistance flatness (RON max – RON min) measured at identical VCC and temperature VCC = 3.3V; VI = 0V to 0.4V for AUXP; VI = 2.7V to 3.6V for AUXN 1.0 Ω VAUXP_DC _CM AUX Channel DC common-mode voltage for AUXP and SBU1. VCC = 3.3V 0 0.4 V VAUXN_D C_CM AUX Channel DC common-mode voltage for AUXN and SBU2 VCC = 3.3V 2.7 3.6 V 5.6 Timing Requirements MIN NOM MAX UNIT I2C Timing fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 µs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (VI2C/ 5.5V) 120 ns tSUSTO Setup time for STOP condition 0.26 µs CBUS Capacitive load for each bus line 100 pF HPDIN and CTL1 tCTL1_DEBO UNCE CTL1 and HPDIN debounce time when transitioning from H to L. DP lanes disabled if low is greater than minimum value. 2.5 ms USB3.1 and DisplayPort mode transition requirement GPIO mode tGP_USB_4D P Minimum overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-lane DisplayPort mode or vice versa 4 µs Power-on timings td_pg VCC(MIN) to Internal power good asserted high 500 µs tcfg_su CFG pins setup 350 µs tcfg_hd CFG pin hold 10 µs tctl_db CTL[1:0] and FLIP pin debounce 16 ms tVCC_RAMP VCC supply ramp requirement 0.1 100 ms 5.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT USB 3.1 tIDLEEntry Delay from U0 to electrical idle 0.16 ns tIDLEExit_U 1 U1 exist time: break in electrical idle to the transmission of LFPS 0.16 ns tIDLEExit_U 2U3 U2/U3 exit time: break in electrical idle to transmission of LFPS 5 µs TUSB1044A SLLSG07 – MARCH 2025 www.ti.com 10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: TUSB1044A |
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