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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TUSB1044AI датащи(PDF) 43 Page - Texas Instruments |
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TUSB1044AI датащи(HTML) 43 Page - Texas Instruments |
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43 / 66 page  Table 8-9. DisplayPort_2 Register Field Descriptions (continued) Bit Field Type Reset Description 0 DP0_DISABLE R/W 0h When AUX_SNOOP_DISABLE = 1b, this field can be used to enable or disable DP lane 0. When AUX_SNOOP_DISABLE = 0b, changes to this field have no effect on lane 0 functionality. 0h = DP Lane 0 enabled. 1h = DP Lane 0 disabled. 8.1.8 DFP2_EQ Register (Offset = 20h) [Reset = 00h] DFP2_EQ is shown in Table 8-10. Return to the Summary Table. Table 8-10. DFP2_EQ Register Field Descriptions Bit Field Type Reset Description 7-4 DTX2EQ_SEL R/W 0h Field selects the EQ for the DTX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DTX2P/N pins based on the value written to this field. 3-0 DRX2EQ_SEL R/W 0h Field selects the EQ for the DRX2P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DRX2P/N pins based on the value written to this field. 8.1.9 DFP1_EQ Register (Offset = 21h) [Reset = 00h] DFP1_EQ is shown in Table 8-11. Return to the Summary Table. Table 8-11. DFP1_EQ Register Field Descriptions Bit Field Type Reset Description 7-4 DTX1EQ_SEL R/W 0h Field selects the EQ for the DTX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DTX1P/N pins based on the value written to this field. 3-0 DRX1EQ_SEL R/W 0h Field selects the EQ for the DRX1P/N pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DEQ[1:0] pins. When EQ_OVERRIDE = 1b, the software can change the EQ setting for the DRX1P/N pins based on the value written to this field. 8.1.10 USB3_MISC Register (Offset = 22h) [Reset = 04h] USB3_MISC is shown in Table 8-12. Return to the Summary Table. Table 8-12. USB3_MISC Register Field Descriptions Bit Field Type Reset Description 7 CM_ACTIVE RH 0h Compliance mode status. 0h = Not in USB3.2 compliance mode. 1h = In USB3.2 compliance mode. 6 LFPS_EQ R/W 0h Controls whether the EQ settings based on URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL applies to the received LFPS signal. 0h = EQ set to 0 when receiving LFPS 1h = EQ set by the related registers when receiving LFPS. www.ti.com TUSB1044A SLLSG07 – MARCH 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TUSB1044A |
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