TUSB1044AI datasheet(37/66 Pages) TI1

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7.4.7 USB3.1 Modes

The TUSB1044A monitors the physical layer conditions like receiver termination, electrical idle, LFPS, and

SuperSpeed signaling rate to determine the state of the USB3.1 interface. Depending on the state of the USB

3.1 interface, the TUSB1044A can be in one of four primary modes of operation when USB 3.1 is enabled (CTL0

= H or CTLSEL0 = 1b1): Disconnect, U2/U3, U1, and U0.

The disconnect mode is the state in which TUSB1044A has not detected far-end termination on both upstream

facing port (UFP) or downstream facing port (DFP). The disconnect mode is the lowest power mode of each of

the four modes. The TUSB1044A remains in this mode until far-end receiver termination has been detected on

both UFP and DFP. The TUSB1044A immediately exits this mode and enters U0 mode when far-end termination

is detected.

When in U0 mode, the TUSB1044A redrives all traffic received on UFP and DFP. U0 is the highest power mode

of all USB3.1 modes. The TUSB1044A remains in U0 mode until electrical idle occurs on both UFP and DFP.

Upon detecting electrical idle, the TUSB1044A immediately transitions to U1.

The U1 mode is the intermediate mode between U0 mode and U2/U3 mode. In U1 mode, the TUSB1044A

UFP and DFP receiver termination remain enabled. The UFP and DFP transmitter DC common-mode voltage is

maintained. The power consumption in U1 is similar to power consumption of U0.

Next to the disconnect mode, the U2 and U3 mode is next lowest power state. While in this mode, the

TUSB1044A periodically performs far-end receiver detection. Anytime the far-end receiver termination is not

detected on either UFP or DFP, the TUSB1044A leaves the U2 and U3 mode and transition to the disconnect

mode. The device also monitors for a valid LFPS. Upon detection of a valid LFPS, the TUSB1044A immediately

transitions to the U0 mode. In U2 and U3 mode, the TUSB1044A receiver terminations remains enabled, but the

TX DC common-mode voltage is not maintained.

When SLP_S0# is asserted low, the TUSB1044A disables Receiver Detect functionality. While SLP_S0# is

low and TUSB1044A is in U2 and U3, the TUSB1044A disables LOS and LFPS detection circuitry and RX

termination for both channels remains enabled. This allows even lower TUSB1044A power consumption while in

the U2 and U3 mode. When SLP_S0# is asserted high, the TUSB1044A again starts performing far-end receiver

detection as well as monitors the LFPS so the device can know when to exit the U2 and U3 mode.

When SLP_S0# is asserted low and the TUSB1044A is in disconnect mode, the TUSB1044A remains in

disconnect mode and never performs far-end receiver detection. This allows even lower TUSB1044A power

consumption while in the disconnect mode. When SLP_S0# is asserted high, the TUSB1044A again starts

performing far-end receiver detection so the device can know when to exit disconnect mode.

7.5 Programming

For further programmability, the TUSB1044A can be controlled using I2C. The SCL and SDA terminals are used

for I2C clock and I2C data, respectively.

Table 7-10. I2C Target Address

TUSB1044A I2C Target Address

UEQ1/A1

PIN LEVEL

UEQ0/A0

PIN LEVEL

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(W/R)

0/1

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TUSB1044A

SLLSG07 – MARCH 2025

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