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TMP86FS28DFG датащи(PDF) 169 Page - Toshiba Semiconductor |
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TMP86FS28DFG датащи(HTML) 169 Page - Toshiba Semiconductor |
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169 / 272 page ![]() Page 157 TMP86FS28DFG SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted. That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF> is cleared to “0” when a transfer is completed. When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to “0”. When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will end. If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”. Figure 11-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock) Figure 11-8 Transfer Mode (Example: 8bit, 1word transfer, External clock) a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 a0 DBR b a Clear SIOS Write (a) Write (b) SCK pin (Output) SO pin INTSIO interrupt SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SIOF> SIOSR<SEF> a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 a0 DBR b a Clear SIOS Write (a) Write (b) SCK pin (Input) SO pin INTSIO interrupt SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> |
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