TMP86FS28DFG datasheet(170/272 Pages) TOSHIBA

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Page 158

11. Synchronous Serial Interface (SIO)

11.6 Transfer Mode

TMP86FS28DFG

Figure 11-9 Transmiiied Data Hold Time at End of Transfer

11.6.2 4-bit and 8-bit receive modes

After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The

data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word

of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the

number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is

generated to request that these data be read out. The data are then read from the data buffer registers by the

interrupt service program.

When the internal clock is used, and the previous data are not read from the data buffer register before the

next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.

A wait will not be initiated if even one data word has been read.

Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,

during SIO do not use such DBR for other applications.

When an external clock is used, the shift operation is synchronized with the external clock; therefore, the

previous data are read before the next data are transferred to the data buffer register. If the previous data have

not been read, the next data will not be transferred to the data buffer register and the receiving of any more data

will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay

between the time when the interrupt request is generated and when the data received have been read.

The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full

interrupt service program.

When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>

cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has

ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiv-

ing is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIO-

INH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is

ignored, and it is not required to be read out.)

If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be

cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to

“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which

occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read

out.

Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the

transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the trans-

fer mode.

MSB of last word

tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)

tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)

SCK pin

SO pin

SIOSR<SIOF>

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