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TMP86FS28DFG датащи(PDF) 81 Page - Toshiba Semiconductor |
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TMP86FS28DFG датащи(HTML) 81 Page - Toshiba Semiconductor |
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81 / 272 page ![]() Page 69 TMP86FS28DFG 5.9 Port P8 (P80 to P87) Port P8 is an 8-bit input/output port that can also be used for LCD segment output. A reset initializes the output latch (P8DR) to “1”, the Pch control (P8OUTCR) to “0”, and the LCD output control register (P8LCR) to “0”. To use a pin in Port P8 as an input port, set P8DR to “1” and then set the corresponding bit in P8LCR and P8OUTCR to “0”. To use a pin in Port P8 as an LCD segment output, set the corresponding bit in P8LCR to “1”. The output circuit of Port P8 can be set either as sink open-drain output (“0”) or CMOS output (“1”) individually for each bit in P8OUTCR. Port P8 has a separate data input register. The output latch state can be read from the P8DR register, and the pin state can be read from the P8PRD register. Note: An asterisk (*) indicates that either “1” or “0” can be set. Figure 5-10 Port P8 Table 5-11 Register Programming for Port P8 (P80 to P87) Function Port Input P8DR P8OUTCR P8LCR Port input “1” “0” “0” Port “0” output “0” Set as appropriate. “0” Port “1” output “1” “0” LCD segment output * * “1” Data input (P8PRD) Output latch read (P8DR) STOP OUTEN P8OUTCRi input Data output (P8DR) P8OUTCRi P8i Note) i = 7~0 DQ DQ LCD data output P8LCRi DQ P8LCRi input Output latch |
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