TMP86FS28DFG datasheet(165/272 Pages) TOSHIBA

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Page 153

TMP86FS28DFG

Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving.

Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest

address. ( The first buffer address transmitted is 0F60H ).

Note 3: The value to be loaded to BUF is held after transfer is completed.

Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0).

Note 5: *: Don't care

Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.

Note 1: Tf; Frame time, TD; Data transfer time

Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1".

Figure 11-2 Frame time (Tf) and Data transfer time (TD)

11.3 Serial clock

11.3.1 Clock source

Internal clock or external clock for the source clock is selected by SIOCR1<SCK>.

WAIT

Wait control

Always sets "00" except 8-bit transmit / receive mode.

Write

only

00:

Tf = TD(Non wait)

01:

Tf = 2TD(Wait)

10:

Tf = 4TD(Wait)

11:

Tf = 8TD (Wait)

BUF

Number of transfer words

(Buffer address in use)

000:

1 word transfer

0F60H

001:

2 words transfer

0F60H ~ 0F61H

010:

3 words transfer

0F60H ~ 0F62H

011:

4 words transfer

0F60H ~ 0F63H

100:

5 words transfer

0F60H ~ 0F64H

101:

6 words transfer

0F60H ~ 0F65H

110:

7 words transfer

0F60H ~ 0F66 H

111:

8 words transfer

0F60H ~ 0F67H

SIO Status Register

SIOSR

76543

210

(0F69H)

SIOF

SEF

SIOF

Serial transfer operating status moni-

tor

Transfer terminated

Transfer in process

Read

only

SEF

Shift operating status monitor

Shift operation terminated

Shift operation in process

(output)

SCK output

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