TMP86FS28DFG datasheet(84/272 Pages) TOSHIBA

84 / 272 page

Page 72

6. Watchdog Timer (WDT)

6.2 Watchdog Timer Control

TMP86FS28DFG

6.2 Watchdog Timer Control

The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch-

dog timer is automatically enabled after the reset release.

6.2.1 Malfunction Detection Methods Using the Watchdog Timer

The CPU malfunction is detected, as shown below.

1. Set the detection time, select the output, and clear the binary counter.

2. Clear the binary counter repeatedly within the specified detection time.

If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watch-

dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When

WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is

initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.

The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP

mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.

Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH

is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow

time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/

4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the

time set to WDTCR1<WDTT>.

Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection

(WDTCR2), 4EH

: Clears the binary counters.

(WDTCR1), 00001101B

: WDTT

← 10, WDTOUT ← 1

(WDTCR2), 4EH

: Clears the binary counters (always clears immediately before and

after changing WDTT).

Within 3/4 of WDT

detection time

(WDTCR2), 4EH

: Clears the binary counters.

Within 3/4 of WDT

detection time

(WDTCR2), 4EH

: Clears the binary counters.

TMP86FS28DFG датащи(PDF) 84 Page - Toshiba Semiconductor