TMPR3916 datasheet(92/225 Pages) TOSHIBA

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Chapter 3 Graphics Display Controller (GDC)

Preliminary

3-13

3.4

Registers

Overview

Short

Name

Address

Name

Function

DCR

1C050000

display control register

Sets the GDC operations.

SARA/E

1C050010

Layer A/E’s start address register

Specifies the start address of layer A/E on the

frame buffer.

SARB

1C050014

Layer B’s start address register

Specifies the start address of layer B on the

frame buffer.

SARC

1C050018

Layer C’s start address register

Specifies the start address of layer C on the

frame buffer.

SARD

1C05001C

Layer D’s start address register

Specifies the start address of layer D on the

frame buffer.

MWRA/E

1C050020

Layer A/E’s Memory Width register

Specifies the line width of layer A/E on the frame

buffer.

MWRB

1C050024

Layer B’s Memory Width register

Specifies the line width of layer B on the frame

buffer.

MWRC

1C050028

Layer C’s Memory Width register

Specifies the line width of layer C on the frame

buffer.

MWRD

1C05002C

Layer D’s Memory Width register

Specifies the line width of layer D on the frame

buffer.

HTN

1C050030

Layer A/E, B, C’s horizontal transfer

number register

Sets the number of display dots for one line

divided by 32. For layers A/E, B, and C.

HTND

1C050034

Layer D’s horizontal transfer number

Sets the number of display dots for one line

divided by 32. For layer D.

HDSER

1C050038

Layer A/E, B, C’s horizontal display start /

end register

Sets the layer’s display position and the number

of display dots for layers A/E, B, and C.

HDSERD

1C05003C

Layer D’s horizontal display start / end

Sets the horizontal display position and the

number of display dots for layer D.

HCR

1C050040

horizontal cycle register

Specifies the total number of dots within a

horizontal cycle.

HSWR

1C050044

horizontal synchronization pulse width

Specifies the horizontal sync signal pulse width

using the number of dot clocks.

VCR

1C050048

vertical cycle register

Specifies the total number of lines within a

vertical cycle.

VSWR

1C05004C

vertical synchronization pulse width

Specifies the vertical sync signal pulse width

using the number of lines.

VDSR

1C050050

Layer A/E, B, C’s vertical display start

Sets the vertical display start position for layers

A/E, B, and C.

VDSRD

1C050054

Layer D’s vertical display start register

Sets the vertical display start position for layer D.

VDER

1C050058

Layer A/E, B, C’s vertical display end

Sets the vertical display end position for layers

A/E, B, and C. The difference VDER – VDSR

defines the number of display dots for layers A/E,

B, and C.

VDERD

1C05005C

Layer D’s vertical display end register

Sets the vertical display end position for layer D.

The different VDERD – VDSRD defines the

number of display dots for layer D.

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