TMPR3916 datasheet(70/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-21

When RWT = 0xF and RPWT = 0x3, the ACK* pin becomes an input and the data transaction

is completed upon assertion of the ACK* signal by the accessed memory.

2.6.3.2

Page Mode ROM setting

Please note the following before setting the registers to drive memories in burst mode.

•

Normal Sub-mode

A channel enters this mode when the following conditions exist: RPM = 00 and

(RPWT:RWT[3:0])! = 0x3Fh.

In this mode the ACK*/READY pin is an ACK* output and the cycle is terminated based

on a 6-bit wait counter. The 6-bit wait counter is the concatenation of the RPWT and RWT

fields. Access time can be programmed to allow for 0 to 62 wait states. (Note:

(RPWT:RWT[3:0] = 0x3Fh indicates external ACK* sub-mode.)

•

External ACK* Sub-mode

A channel enters this mode when the following conditions exist: RPM =00 and

(RPWT:RWT[3:0] = 0x3Fh.

In this mode the ACK*/READY pin is an ACK* input and the cycle is terminated by the

external device. The ACK* input is synchronized before it is fed to the internal state

machine. See section ACK* input timing for more details.

•

Page Sub-mode

A channel enters this mode when the following conditions exist: RPM! = 00.

In this mode the ACK*/READY pin is an ACK* output and the cycle is terminated based

on either the RPWT or RWT wait counter. The mode specifically targets Page Mode ROMs.

During single cycle access, or the first word of a burst access, the 4-bit RWT field determines

the access time. The access time can be programmed to allow for 0 to 15 wait states. During

subsequent burst cycle accesses, the 2-bit RPWT field determines the access time and can be

programmed to allow for 0 to 3 wait states.

There are 3 different Page Mode Burst size settings allowed in the RPM field. When the

Page Mode burst size is less than the CPU burst size, the channel will break access such that

the 4-bit RWT field is always used on the programmed Page Mode boundary. In Page Mode

the RWT time must be greater than or equal to the RPWT time or undetermined results may

occur.

•

16-bit Bus Operation

In the case of 16-bit mode if a single cycle is run from the G-Bus that requires a single byte

or half word that is contained within one 16-bit word then only a single 16-bit access is run

on the external bus. Otherwise two 16-bit accesses are executed externally. In the case of 16-

bit mode, if a burst cycle is run from the G-Bus, two 16-bit cycles will be run for each of the

burst accesses regardless of the fact that the internal byte enable signal is requesting a byte,

half word or any other combination of internal byte enable signal that is not a full 32-bit

word.

In 16-bit mode the maximum channel size is 512 Mbytes.

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