TMPR3916 datasheet(55/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-6

2.3

Ports of Memory Controller

The SDRAM controller externally connects up to two channels of SDRAM memory. Each of the two

SDRAM controller channels has its own organization register and can support different device sizes and

organization. The timing settings are shared for both channels and must be the same for both channels.

Refresh is conducted on both channels in parallel.

The memory channels share the memory data, address and control busses with the exception of the chip-

select signal, which is wired individually for each channel. Each channel must be connected with a width of

32 bits. Devices with organizations of 4, 8, 16 and 32 bit width can be used as long as the connected devices

jointly form a 32 bit channel. The following table summarizes the externally connected memory signals.

Signal

Type

Description

SYSCLK

OUT

DRAM Clock

A[14:2]

OUT

Row/Column Address Bus,

connect to A at the SDRAM device

A[16:15]

OUT

Bank Address Bus,

connect to BA at the SDRAM device

RAS*

OUT

Row Access Strobe signal

CAS*

OUT

Column Access Strobe signal

WE*

OUT

Write Enable Signal

CKE

OUT

Clock Enable Signal for SDRAM

CS*[1:0]

OUT

Chip Select Signal, one for each SDRAM channel

CS[0] => channel X

CS[1] => channel Y

D[31:0]

IN/OUT

Data Bus,

connect to DQ at the SDRAM device

BE[3:0]

OUT

Output Mask,

connect to DQM at the SDRAM device

2.4

Registers

The following registers are used for configuration and operation of the TMPR3916 memory channels 2 to

5 via MEMC. For channels 0 and 1 (SDRAM) refer to section 2.5.4.

Device

(short name)

Physical

Address (hex)

Function

RCCR2

1C02 0008H

ROM Control Register Channel 2

RCCR3

1C02 000CH

ROM Control Register Channel 3

RCCR4

1C02 0010H

ROM Control Register Channel 4

MEMC

RCCR5

1C02 0014H

ROM Control Register Channel 5

DCCR

1C02 8000H

SDRAM Configuration Register

DCBA

1C02 8004H

SDRAM Base Address Register

DCAM

1C02 8008H

SDRAM Address Mask Register

SDRAM

DCTR

1C02 800CH

SDRAM Timing Register

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