TMPR3916 datasheet(63/225 Pages) TOSHIBA

63 / 225 page

Chapter 2 Memory Controller (MC)

Preliminary

2-14

Bit

Name

Function

Reset

Value

R/W

17:16

WRL

Write Recovery Latency

This setting defines the minimum number of cycles, from the point

where the last word has been written until the “precharge” command

is issued. This setting has to match the write recovery time (tWR) of

the selected SDRAM.

00 = 1 cycle

01 = 2 cycles

10 = 3 cycles

11 = 4 cycles

R/W

15:13

APL

Active to Precharge Latency

This field and the associated timer is used to ensure the Active to

Precharge Latency (tRAS). The register value is used as reload

value for an internal down counter.

PCHG Latency

000 ..010 = Invalid setting

011 = 3 cycles

100 = 4 cycles

101 = 5 cycles

110 = 6 cycles

111 = 7 cycles

111

R/W

12:10

RASL

RAS Latency

This timeframe has to safely match the tRCD time of the selected

SDRAM device. The setting defines the number of cycles between

providing the row address and the column address. This setting is

used as reload value for a 3 bit down counter.

010 = 2 cycles

011 = 3 cycles

100 = 4 cycles

101 = 5 cycles

Others = Invalid setting

011

R/W

9:7

CASL

CAS Latency

This setting defines the number of clock cycles from the time that

the column address is provided (READ, RDA / WRITE, WRA) until

the first data is taken/output from/on the SDRAM data bus.

During the power-up sequence, this value is programmed into the

mode register as it is. For the SDRAM controller this setting is used

as a reload value for an internal down counter. CAS latencies of less

than 2 cycles are not supported!

010 = 2 cycles

011 = 3 cycles

Others = Invalid settings

011

R/W

6:4

PAL

Same Bank Precharge -> Active/Refresh Latency

This setting defines the minimum number of cycles from the point

where the bank is precharged until it is reused (Activate, Refresh).

This timeframe is defined by the tRP time of the selected memory

device. This time will not be taken, if a different bank or a different

memory device is accessed.

010 = 2 cycles

011 = 3 cycles

100 = 4 cycles

101 = 5 cycles

110 = 6 cycles

111 = 7 cycles

Others = Invalid settings

111

R/W

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