TMPR3916 datasheet(64/225 Pages) TOSHIBA

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Chapter 2 Memory Controller (MC)

Preliminary

2-15

Bit

Name

Function

Reset

Value

R/W

3:0

ARL

Auto Refresh To Next Command Latency

This setting defines the number of clocks, which are taken after an

Auto Refresh Command has been issued. This setting is used as a

reload value for a down counter. The counter will prevent any active

SDRAM commands until it is expired.

0000 = Invalid setting

0001 = 3 cycles

0010 = 4 cycles

0011 = 5 cycles

……

1111 = 17 cycles

111

R/W

2.5.5

Software Power-Up Sequence

The picture below shows the software flow that is necessary to initialize the module.

The SDRAM memory typically requires to be held in reset or disabled state until the internal circuits

have stabilized. Software has to ensure that this state is applied for the specified amount of time by not

enabling the SDRAM controller during this timeframe. After the configuration registers have been

sequentially configured, a power-up cycle needs to be scheduled by writing a “1” value to the PWR bit

in the DCCR register. Finally, the SDRAM controller and the utilized channels needs to be enabled to

start the initialization. The PWR bit can be read to determine the end of the Power-Up sequence. During

the power-up procedure, this flag will be read as “1”. It is cleared, when the power-up procedure

completes.

Software Flow of Initialization:

Wait for at least 200

µs

Reset

Configure Control Register

(DCCR)

Configure Timing Register

(DCTR)

Configure Address Mapping

(DCAM)

Set PWR in DCCR

Enable the module by asserting

the ENA bit in DCCR

PWR

cleared?

DRAM ready for usage

Yes

Configure Address Mapping

(DCBA)

Figure 2.5.2 SDRAM Power-up Software Sequence Flow Chart

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