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ELANSC310 датащи(PDF) 117 Page - Advanced Micro Devices |
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ELANSC310 датащи(HTML) 117 Page - Advanced Micro Devices |
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117 / 119 page ![]() Élan™SC310 Microcontroller Data Sheet 117 PREL IMINARY Notes: The appropriate timings above are also valid for the Bidirectional Parallel Port mode. Table 61. EPP Data Register Read Cycle (See Figure 50) Symbol Parameter Description Max Min Unit t1 AFDT delay from PPDCS active 1.8 1.1 ns t2 AFDT active pulse width (no wait states) 450 448 ns t3 AFDT High to Low recovery 1000 ns t4 Read data valid delay 25.3 ns t5 Read data hold time 2.3 ns t6 PPDCS delay from IOR active 6.8 ns t7 PPDCS delay from AFDT inactive 3.7 1.8 ns t8 PPDCS delay from IOR inactive 4.2 ns t9 BUSY (inactive) hold from AFDT High 0 ns t1 t2 t3 t4 t5 t6 t8 t7 t9 Data Valid AFDT STRB D7–D0 PPDCS PPOEN IOR IOW BUSY Figure 50. EPP Data Register Read Cycle |
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