ELANSC310 datasheet(37/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

JTAG BOUNDARY SCAN INTERFACE

The ÉlanSC310 microcontroller provides an IEEE Std

1149.1-1990 (JTAG) compliant Standard Test Access

Port (TAP) and Boundary-Scan Architecture.

The boundary-scan test logic consists of a boundary

scan register and support logic that are accessed

through the TAP. The TAP provides a simple serial in-

terface that makes it possible to test the microcontroller

and system hardware in a production environment.

The TAP contains extensions that allow a hardware-

development system to control and observe the micro-

controller without interposing hardware between the

microcontroller and the system.

The TAP can be controlled via a bus master. The bus

master can be either automatic test equipment or a

component (PLD) that interfaces to the four-pin test

bus.

The JTAG pins described here are shared pin func-

tions. They are enabled by the JTAGEN signal.

JTAGEN

JTAG Enable (Input; Active High)

This pin enables the JTAG pin functions. When it is

High, the JTAG interface is enabled. When it is Low, the

JTAG pin functions are disabled and the pins are con-

figured to their default functions. See the Pin Designa-

tions, System Interface, and Miscellaneous Interface

tables for the JTAG pin default function descriptions.

For more information, see “System Test and Debug” on

page 64.

[TCK]

Test Clock (Input)

Test clock is a JTAG input clock that is used to access

the test access port when JTAGEN is active.

[TDI]

Test Data Input (Input)

Test data Input is the serial input stream for JTAG scan

input data when JTAGEN is active.

[TDO]

Test Data Output (3-State Output)

Test data Output is the serial output stream for JTAG

scan result data when JTAGEN is active.

[TMS]

Test Mode Select (Input)

Test Mode Select is an input for controlling the Test Ac-

cess Port when JTAGEN is active.

RESET AND POWER

See “Voltage Partitioning” on page 84 for more infor-

mation about power.

AGND

Analog Ground pin

This pin is the ground for the analog circuitry and is bro-

ken out separately from the other GND pins making it

possible to filter AGND in a system that has a lot of

noise on the ground plane. In most applications, AGND

is tied directly to the ground plane with the other ground

pins on the microcontroller.

AVCC

3.3 V (only) Supply Pin

This supply pin provides power to the analog section of

the ÉlanSC310 microcontroller’s internal PLLs. Ex-

treme care should be taken that this supply voltage is

isolated properly to provide a clean, noise-free voltage

to the PLLs.

AVCC is required for battery backup. For more informa-

tion about battery backup, see the

ÉlanTMSC300 and

ÉlanTMSC310 Microcontrollers Solution For Systems

Using a Back-Up Battery Application Note, order

#20746.

GND

System Ground Pins

These pins provide electric grounding to all non-analog

sections of the ÉlanSC310 microcontroller’s internal

CPU and peripherals.

IORESET

Reset Input (Input; Active Low)

IORESET is an asynchronous hardware reset input

equivalent to POWERGOOD in the PC/AT system ar-

chitecture. Asserting this signal does not reset the RTC

RAM invalid bit.

Asserting IORESET without asserting RESIN causes

the ÉlanSC310 microcontroller to enter Micro Power

Off mode. For more information, see “Micro Power Off

Mode” on page 46.

RESIN

Master Reset (Input; Active Low)

RESIN indicates that main power is initially being ap-

plied to the ÉlanSC310 microcontroller for the first time.

When this signal is asserted, the RTC and Internal reg-

isters are reset.

The RESIN signal supersedes the IORESET signal.

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