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ELANSC310 датащи(PDF) 112 Page - Advanced Micro Devices

номер детали ELANSC310
подробное описание детали  Single-Chip, 32-Bit, PC/AT Microcontroller
PDF  119 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
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ELANSC310 датащи(HTML) 112 Page - Advanced Micro Devices

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Élan™SC310 Microcontroller Data Sheet
PREL IMINARY
Notes:
These timings may be modified via the MMS Memory Wait State 1 Register, Index 62h, and the Command Delay Register, Index
60h. (See the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665.)
1. These timings apply only to the B4 version of the ÉlanSC310 microcontroller. The timings for the B3 version are t2b = 0 ns,
t3b = 550 ns, t11b = -2 ns, and t13 = -4 ns.
Table 58.
ISA I/O 8-Bit Read/Write Cycle (See Figure 47)
Symbol
Parameter Description
Notes
Preliminary
Units
Min
Max
t1a
SA stable to IOW active
200
ns
t1b
SA stable to IOR active
150
ns
t2a
SA hold from IOW inactive
50
ns
t2b
SA hold from IOR inactive
1
50
ns
t3a
IOW pulse width
450
ns
t3b
IOR pulse width
1
505
ns
t4a
IOW active to IOCHRDY inactive
300
ns
t4b
IOR active to IOCHRDY inactive
350
ns
t5a
IOW hold from IOCHRDY active
110
ns
t5b
IOR hold from IOCHRDY active
160
ns
t6
RDDATA setup to command inactive
40
ns
t7
RDDATA hold from command inactive
0
ns
t8
WRDATA setup to command inactive
400
ns
t9
WRDATA hold from command inactive
50
ns
t10
DBUFOE active from command
5
ns
t11a
DBUFOE hold from command Write
50
ns
t11b
DBUFOE hold from command Read
1
50
ns
t12
ENDIRH, ENDIRL setup to IOR
150
ns
t13
ENDIRH, ENDIRL hold from IOR
150
ns
t14
BALE pulse width
50
ns



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