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ELANSC310 датащи(PDF) 116 Page - Advanced Micro Devices

номер детали ELANSC310
подробное описание детали  Single-Chip, 32-Bit, PC/AT Microcontroller
PDF  119 Pages
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC310 датащи(HTML) 116 Page - Advanced Micro Devices

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Élan™SC310 Microcontroller Data Sheet
PREL IMINARY
Notes:
The appropriate timings above are valid for the Bidirectional Parallel Port mode also. Timings t13 and t14 are also valid for the
Unidirectional Parallel Port mode. (PPDCS is PPWDE in Unidirectional mode.)
Table 60.
EPP Data Register Write Cycle (See Figure 49)
Symbol
Parameter Description
Max
Min
Units
t0
AFDT delay from IOW active
8.4
4.9
ns
t1
AFDT delay from PPDCS active
1.8
1.1
ns
t2
AFDT delay from PPOEN active
1.0
0.8
ns
t3
AFDT active pulse width (no wait states added)
450
448
ns
t4
AFDT High to Low recovery
1000
ns
t5
AFDT Low to STRB Low
–0.2
ns
t6
STRB delay from PPDCS active
1.6
0.9
ns
t7
STRB delay from PPOEN active
0.8
0.6
ns
t8
AFDT High to STRB High delay
–2.4
–1.4
ns
t9
STRB Low to data valid delay
3.7
ns
t10
STRB High to data valid hold
4.0
ns
t11
PPOEN delay from IOW active
7.4
ns
t12
PPOEN delay from IOW inactive
1.1
ns
t13
PPDCS delay from IOW active
6.6
ns
t14
PPDCS delay from IOW inactive
4.3
ns
t15
AFDT hold from BUSY High
139
129
ns
t16
BUSY Low delay from AFDT active
307
ns
t3
t1
t2
t0
t15
t4
t5
t7
t8
t9
t10
t16
t11
t12
t13
t14
Valid Data
AFDT
STRB
D7–D0
BUSY
PPOEN
PPDCS
IOW
IOR
t6
Figure 49.
EPP Data Register Write Cycle



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