ELANSC310 datasheet(45/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

Notes:

All power management features will be disabled when AC power is detected via the ACIN pin being High. A register is provided

to implement “software ACIN” by writing 1 to bit 5 in the Miscellaneous 6 Register, Index 70h.

The DMA clock can be stopped except during DMA transfers. The Function Enable Register, Index B0h, controls this function.

The CPU clock speed in Low-Speed PLL mode is selectable, (see the PMU Control 3 Register, Index ADh).

The CPU Clock speed:

1. Can be programmed to run intermittently (on IRQ0) at 9.2 MHz.

2. Programmable option (but not on per-clock basis; i.e., all clocks with this note are controlled by a single ON/OFF select for

that PMU mode).

3. Programmable option, will reflect setting in Suspend mode.

4. Can be programmed to run at 9.2 MHz during temporary-on NMI/SMI handlers.

PMC and PGP Pins

The ÉlanSC310 microcontroller supports five power

management control (PMC) pins and four programma-

ble general purpose (PGP) pins. The PMC pins can be

used to control the VCC rails of peripheral devices. The

PMC pins are related to the operating modes of the

ÉlanSC310 microcontroller PMU. The PGP pins can be

used as general I/O chip selects for various uses.

The PMC4–PMC0 pins are controlled by Configuration

Registers at Indexes 80h, 81h, ABh, and ACh. Each

pin can be programmed to be activated upon entry into

any of the PMU modes or driven directly by software.

PMC0 can be activated when the system is in High-

Speed PLL or Low-Speed PLL modes; PMC1 when the

system is in Doze mode; PMC2 when the system is in

Sleep mode; PMC3 and PMC4 when the system is in

Suspend mode; or just about any other combination.

These pins can then be used by the system designer to

shut off power to particular peripherals when the sys-

tem enters certain modes, just as internal clocks are

slowed or stopped in these modes. Upon the rising

edge of RESIN, PMC0, PMC1, PMC2, and PMC4 are

Table 21.

PMU Modes

Mode

Description

Power On

After Power-on reset, system enters High-Speed PLL mode.

High-Speed PLL

The system will be in this mode as long as activities are detected by activity monitor (described in the Pro-

grammable Activity Mask Registers, Indexes 08h, 75h, and 76h).

Low-Speed PLL

The system will enter this mode from High-Speed PLL mode after a programmable 1/512 s to 1/2 s, or

1/16 s to 16 s of inactivity.

Doze

The system will enter this mode from Low-Speed PLL mode after a programmable 1/16 s to 16 s, or

1/2 s to 128 s of inactivity.

Sleep

The system will enter this mode from Doze mode after a programmable 4 s to 17 minutes of inactivity.

Suspend

The system will enter this mode from Sleep mode after a programmable 1/16 s to 16 s of inactivity.

Off

The system will enter this mode from Suspend mode after a programmable 1 to 256 minutes of inactivity.

Table 22.

Internal Clock States

Mode

High-Speed

CPU CLK

Low-Speed

CPU CLK

VIDEO CLK

DMA CLK

SYSCLK

8254 CLK

(Timer)

16450 CLK

(UART)

High-Speed

PLL

33/25/20 MHz

9.2 MHz

14.336 MHz

4.6 MHz

9.2 MHz

1.19 MHz

1.8432 MHz

Low-Speed

PLL

4.608/2.304/

1.152/0.567 MHz

4.608/2.304/

1.152/0.567 MHz

14.336 MHz

2.3/1.2/

0.58/0.29

MHz

9.2 MHz

1.19 MHz

1.8432 MHz

Doze

DC1

14.3 MHz/DC2

DC1

9.2 MHz/DC2 1.19 MHz/DC2 1.8 MHz/DC2

Sleep

9.2 MHz/DC4

14.3 MHz/DC2 4.6 MHz/DC4

1.19 MHz/DC2 1.8 MHz/DC2

Suspend

9.2 MHz/DC4

14.3 MHz/DC2 4.6 MHz/DC4

1.19 MHz/DC2 1.8 MHz/DC2

Off

9.2 MHz/DC4

14.3 MHz/DC3 4.6 MHz/DC4

1.19 MHz/DC3 1.8 MHz/DC3

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