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TEST датащи(PDF) 13 Page - List of Unclassifed Manufacturers

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подробное описание детали  Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
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PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
13 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
On power-up or reset, all registers return to default values.
Fig 9.
Simplified schematic of the I/Os (P0 to P7)
INTERRUPT
MASK
VDD(P)
P0 to P7
output port
register data
configuration
register
DQ
CK
Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
002aah089
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
VDD(P)
ESD
protection
diode
input port
latch
DQ
EN
LATCH
read pulse
input latch
register
DQ
CK
FF
data from
shift register
write input
latch pulse



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