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TEST датащи(PDF) 32 Page - List of Unclassifed Manufacturers

номер детали TEST
подробное описание детали  Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
PDF  49 Pages
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PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
32 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
15. Parameter measurement information
Table 26.
Switching characteristics
Over recommended operating free air temperature range; CL  100 pF; unless otherwise specified. See Figure 33.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
tv(INT)
valid time on pin INT
from P port to INT
-1-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-1-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
a. SDA load configuration
b. Transaction format
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR
 10 MHz; Z
o =50 ; tr/tf  30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 13.
Fig 31. I2C-bus interface load circuit and voltage waveforms
002aag977
DUT
CL = 50 pF
RL = 1 kΩ
SDA
VDD(I2C-bus)
STOP
condition
(P)
Data
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
R/W
Bit 0
(LSB)
Address
Bit 1
Address
Bit 7
(MSB)
START
condition
(S)
STOP
condition
(P)
two bytes for read Input port register(1)
002aag952
tLOW
tHIGH
tr
tf
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
tSP
tBUF
tf
tHD;STA
tr
SCL
SDA
tSU;DAT
tHD;DAT
tf(o)
tVD;ACK
tVD;DAT
tVD;ACK
tSU;STA
tSU;STO
002aag978
repeat START condition
STOP condition



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