TEST datasheet(31/49 Pages) ETC

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PCAL6408A

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Product data sheet

Rev. 3 — 18 September 2013

31 of 49

NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander

14. Dynamic characteristics

Table 24.

I2C-bus interface timing requirements

Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.

Symbol

Parameter

Conditions

Standard-mode

I2C-bus

Fast-mode I2C-bus

Unit

Min

Max

Min

Max

fSCL

SCL clock frequency

100

400

kHz

tHIGH

HIGH period of the SCL clock

0.6

s

tLOW

LOW period of the SCL clock

4.7

1.3

s

tSP

pulse width of spikes that must

be suppressed by the input filter

tSU;DAT

data set-up time

250

100

tHD;DAT

data hold time

rise time of both SDA and SCL signals

1000

300

fall time of both SDA and SCL signals

300



(VDD /5.5 V)

300

tBUF

bus free time between a STOP and

START condition

4.7

1.3

s

tSU;STA

set-up time for a repeated START

condition

4.7

0.6

s

tHD;STA

hold time (repeated) START condition

0.6

s

tSU;STO

set-up time for STOP condition

0.6

s

tVD;DAT

data valid time

SCL LOW to

SDA output valid

-3.45

0.9

s

tVD;ACK

data valid acknowledge time

ACK signal from

SCL LOW to

SDA (out) LOW

-3.45

0.9

s

Table 25.

Reset timing requirements

Over recommended operating free air temperature range, unless otherwise specified. See Figure 34.

Symbol

Parameter

Conditions

Standard-mode

I2C-bus

Fast-mode

I2C-bus

Unit

Min

Max

Min

Max

tw(rst)

reset pulse width

trec(rst)

reset recovery time

200

trst

reset time

600

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