PCAL6408A

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© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 18 September 2013

16 of 49

NXP Semiconductors

PCAL6408A

Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander

8.2 Read commands

To read data from the PCAL6408A, the bus master must first send the PCAL6408A

address with the least significant bit set to a logic 0 (see Figure 7 for device address). The

command byte is sent after the address and determines which register is to be accessed.

After a restart the device address is sent again, but this time the LSB is set to a logic 1.

Data from the register defined by the command byte then is sent by the PCAL6408A (see

Figure 12 and Figure 13).

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no

limit on the number of data bytes received in one read transmission, but on the final byte

received the bus master must not acknowledge the data.

Fig 12. Read from register

A

S

START condition

R/W

acknowledge

from slave

002aaf827

A

acknowledge

from slave

SDA

A

P

acknowledge

from master

DATA (first byte)

slave address

STOP

condition

S

(repeated)

START condition

(cont.)

(cont.)

10000

AD

DR

1

A

0

R/W

acknowledge

from slave

slave address

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

NA

no acknowledge

from master

10000

AD

DR

0

0

data from register

DATA (last byte)

data from register

command byte

00000

0

1 1/0

Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge

phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port

register).

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and

actual data transfer from P port (see Figure 12).

Fig 13. Read Input port register (non-latched)

10000

AD

DR

1

A

S0

slave address

START condition

R/W

acknowledge from slave

002aaf828

data from port

A

acknowledge from master

SDA

1

no acknowledge

from master

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

P

STOP

condition

tv(INT)

trst(INT)

th(D)

tsu(D)

12345678

SCL

9

DATA 1

DATA 5

INT is cleared by

read from port

STOP not needed

to clear INT