PM7375-SC datasheet(75/430 Pages) PMC

75 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.12.1 Clock Synthesis

The transmit clock may be synthesized from a 19.44 MHz or 6.48 MHz reference.

The phase lock loop filter transfer function is optimized to enable the PLL to track

the reference, yet attenuate high frequency jitter on the reference signal. This

transfer function yields a typical low pass corner of 1 MHz, above which reference

jitter is attenuated at 3 dB per octave. The design of the loop filter and PLL is

optimized for minimum intrinsic jitter. With a jitter free reference, the intrinsic jitter is

typically less than 0.01 UI RMS when measured using a high pass filter with a 12

kHz cutoff frequency.

9.12.2 Parallel to Serial Converter

The Parallel to Serial Converter (PISO) converts the internal byte serial stream to a

bit serial stream.

9.13

JTAG Test Access Port Interface

The JTAG Test Access Port block provides JTAG support for boundary scan. The

standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions

are supported. The LASAR-155 identification code is 073750CD hexadecimal.

9.14

PCI DMA Controller Interface

The PCI DMA Controller (PCID) block provides an interface to the PCI Local Bus to

facilitate data transfer to and from the LASAR-155. When the LASAR-155 is the

initiator, the PCID uses burst DMA cycles to read or write data on the PCI Bus which

minimizes PCI Host bus traffic. When the LASAR-155 is the target, the PCID allows

the PCI Host to access the LASAR-155's internal registers, to communicate with the

microprocessor or to access external devices when the microprocessor is not

present. Communication with an optional microprocessor is facilitated using a

mailbox scheme.

The PCID block provides two transmit and two receive DMA channels to move

packets to and from the LASAR-155. The receive DMA channels are divided into

management data and packet data channels. The transmit DMA channels are

divided into high priority and low priority channels. The DMA channels support

scatter/gather buffer manipulation to allow for flexible and independent operation

with the PCI Host.

The PCID services the four DMA channels using either a round-robin scheme or a

receive priority scheme. For the round-robin scheme, simultaneous DMA requests

are serviced in a fair rotational manner. For the receive priority scheme, receive

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