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PM7375-SC датащи(PDF) 49 Page - PMC-Sierra, Inc |
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PM7375-SC датащи(HTML) 49 Page - PMC-Sierra, Inc |
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49 / 430 page ![]() PM7375 LASAR-155 DATA SHEET PMC-931127 ISSUE 6 LOCAL ATM SAR & PHYSICAL LAYER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 33 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9]/A[9] D[10]/A[10] D[11]/A[11] D[12]/A[12] D[13]/A[13] D[14]/A[14] D[15]/A[15] I/O 164 167 168 169 170 171 172 173 174 188 189 190 191 192 193 194 For slave mode operation the bi-directional data bus D[15:0] is used during LASAR-155 Microprocessor Interface Port register read and write accesses. Little-endian byte formatting is used. D[15:8] should contain the most significant byte of a word while D[7:0] should contain the least significant byte of a word. For master mode operation, only D[7:0] is used for LASAR-155 Local Bus accesses data transfers. A[15:9] are configured as outputs and supply the most significant seven bits of the address on the LASAR-155 Local Bus. For this mode of operation A[15:9] are updated on the rising edge of PCICLK. Note, D[8] is not used and should be pulled high. A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] I/O 175 176 177 178 179 180 181 186 187 For slave mode operation the address bus A[8:0] is configured as inputs. A[8:0] selects specific Microprocessor Interface Port registers during LASAR-155 register accesses. A[8] is the Test Register Select (TRS) address pin. TRS selects between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses. For master mode operation the A[8:0] bus is configured as an output. A[8:0] supplies the least significant nine bits of the address on the LASAR-155 Local Bus. For this mode of operation A[8:0] are updated on the rising edge of PCICLK. |
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