PM7375-SC datasheet(60/430 Pages) PMC

60 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.2.1 Receive Section Overhead Processor

The Receive Section Overhead Processor (RSOP) provides frame synchronization,

descrambling, section level alarm detection (LOS, OOF,LOF) and performance

monitoring.

While in-frame, the framing bytes (A1, A2) in each frame are compared against the

expected pattern. Out-of-frame is declared when four consecutive frames

containing one or more framing pattern errors have been received. While out-of-

frame, the RSOP depends on the SIPO block to monitor the bit serial data stream

for an occurrence of the framing pattern. When a framing pattern has been

recognized, the RSOP verifies that an error free framing pattern is present in the

next frame before declaring in-frame.

When in-frame, descrambling is performed using the standard generating

polynomial 1 + x6 + x7. Section BIP-8 calculation and verification is automatically

performed with errors accumulated into an internal saturating one second counter.

A loss of signal (LOS) condition is declared when 20 ± 3 µs of all zeros pattern is

detected. LOS is cleared when two valid framing words are detected and during the

intervening time, no LOS condition is detected. A loss of frame (LOF) is declared

when an out-of-frame (OOF) condition persists for 3 ms. LOF is cleared when an

in-frame condition persists for a period of 3 ms.

9.2.2 Receive Line Overhead Processor

The Receive Line Overhead Processor (RLOP) provides line level alarm detection

(line FERF, line AIS) and performance monitoring.

Line Far End Receive Failure (FERF) is declared when a 110 binary pattern is

detected in bits 6, 7, and 8 of the K2 byte, for five consecutive frames. FERF is

removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2

byte for five consecutive frames. Line Alarm Indication Signal (AIS) is declared

when a 111 binary pattern is detected in bits 6,7,8 of the K2 byte, for five

consecutive frames. LAIS is removed when any pattern other than 111 is detected

in bits 6, 7, and 8 of the K2 byte for five consecutive frames.

Line BIP-24/8 calculation and verification is automatically performed with errors

accumulated into an internal saturating one second (STS-3c (STM-1) rate) counter.

Accumulation of line far end block error (FEBE) indications into an internal

saturating one second (STS-3c (STM-1) rate) counter is also provided.

PM7375-SC датащи(PDF) 60 Page - PMC-Sierra, Inc